学校代码： 10246 学号：082052067 復旦大屡 硕士学位论文 频率综合器中分频器的研究与设计 院 系： 微电子研究院 专 业： 微电子学与固体电子学 姓 名： 黄兆磊 指导教师： 唐长文 副教授 完成日期： 2011年5月20日
学校代码： 10246 学 号： 082052067 硕 士 学 位 论 文 频率综合器中分频器的研究与设计 院 系： 微电子研究院 专 业： 微电子学与固体电子学 姓 名： 黄兆磊 指 导 教 师： 唐长文 副教授 完 成 日 期： 2011 年 5 月 20 日
目录 摘要… Abstract........ …V 第一章绪论… 1.1研究背景… …1 1.2频率综合器的结构 …1 1.3分频器在频率综合器的作用…2 1.4研究内容及贡献… 3 1.5论文的组织结构…3 第二章分频器的研究… …4 2.1多模可编程分频器… …4 2.1.1可预置数的可编程分频器… …4 2.1.2 Pulse-Swallow型可编程分频器…5 2.1.3基于2/3分频单元的多模可编程分频器 6 2.2预分频器 6 2.2.1同步预分频器 .6 2.2.2异步逻辑的预分频器… …8 2.2.3相位开关型预分频器[16]… …9 2.3高速电路结构 …10 2.3.1TSPC电路… …10 2.3.2电流模式逻辑(CML)… …12 第三章可编程分频器设计… …14 3.1可编程分频器结构… …14 3.2P和S的实现方式… …14 3.2.1可编程分频器的分频范围…。 …14 3.2.2P和S的实现方式…。 …15 3.34/4.5双模预分频器… …17 3.3.14/4.5型双模预分频器结构… …18 3.3.2时序问题… …21 3.4可编程计数器… 23 3.4.1P计数器… …24 3.4.2S计数器 a. 24 3.4.3 bitcell… 28 3.5其它模块电路…30
目录 摘要············································································································III Abstract ··································································································· IV 第一章 绪论 ······························································································1 1.1 研究背景 ························································································1 1.2 频率综合器的结构 ··········································································1 1.3 分频器在频率综合器的作用····························································2 1.4 研究内容及贡献··············································································3 1.5 论文的组织结构··············································································3 第二章 分频器的研究··················································································4 2.1 多模可编程分频器 ··········································································4 2.1.1 可预置数的可编程分频器·····················································4 2.1.2 Pulse-Swallow型可编程分频器············································5 2.1.3 基于 2/3 分频单元的多模可编程分频器································6 2.2 预分频器 ························································································6 2.2.1 同步预分频器·······································································6 2.2.2 异步逻辑的预分频器····························································8 2.2.3 相位开关型预分频器[16]······················································9 2.3 高速电路结构 ···············································································10 2.3.1 TSPC电路 ·········································································10 2.3.2 电流模式逻辑(CML)···························································12 第三章 可编程分频器设计 ········································································14 3.1 可编程分频器结构 ········································································14 3.2 P和S的实现方式 ··········································································14 3.2.1 可编程分频器的分频范围···················································14 3.2.2 P和S的实现方式································································15 3.3 4/4.5 双模预分频器 ······································································17 3.3.1 4/4.5 型双模预分频器结构·················································18 3.3.2 时序问题············································································21 3.4 可编程计数器 ···············································································23 3.4.1 P计数器·············································································24 3.4.2 S计数器·············································································24 3.4.3 bitcell·················································································28 3.5 其它模块电路 ···············································································30 I
3.5.1CML锁存器… …30 3.5.2uX电路… 31 3.5.3组合逻辑电路… 32 3.5.4Sync电路… 32 3.5.5双端转单端电路… …33 36仿真结果… 34 3.6.1预分频器仿真结果 34 3.6.2可编程分频器仿真结果… 35 第四章正交分频器设计… …38 4.1正交信号的实现方法， 38 4.2用于DTV-TUNER的正交分频器… 39 4.2.1应用背景… 39 4.2.2正交分频器结构… 40 4.3二分频电路的设计… 41 4.3.1二分频电路结构… 41 4.3.2CML二分频器的动态特性 42 4.3.3电路设计考虑… 43 4.4其它模块设计… 45 4.4.1多路选择器… …45 4.4.2输出缓冲器 …46 4.5版图设计… 46 第五章测试结果… …48 5.1芯片实现和测试方案… 48 5.2芯片测试结果… 49 5.2.1相位噪声测试结果 49 5.2.2正交相位精度测试… 55 5.2.3功耗估计 59 5.2.4摆幅测试… 59 5.2.5自激振荡频率测试… 60 5.2.6工作频率范围测试 60 第六章总结和展望 …62 6.1工作总结 62 6.2未来展望 62 参考文献… 63 致谢… …65
3.5.1 CML锁存器········································································30 3.5.2 Mux电路············································································31 3.5.3 组合逻辑电路·····································································32 3.5.4 Sync 电路 ·········································································32 3.5.5 双端转单端电路·································································33 3.6 仿真结果 ······················································································34 3.6.1 预分频器仿真结果 ·····························································34 3.6.2 可编程分频器仿真结果 ······················································35 第四章 正交分频器设计············································································38 4.1 正交信号的实现方法·····································································38 4.2 用于DTV-TUNER的正交分频器····················································39 4.2.1 应用背景············································································39 4.2.2 正交分频器结构·································································40 4.3 二分频电路的设计 ········································································41 4.3.1 二分频电路结构·································································41 4.3.2 CML二分频器的动态特性 ··················································42 4.3.3 电路设计考虑·····································································43 4.4 其它模块设计 ···············································································45 4.4.1 多路选择器 ········································································45 4.4.2 输出缓冲器 ········································································46 4.5 版图设计 ······················································································46 第五章 测试结果·······················································································48 5.1 芯片实现和测试方案·····································································48 5.2 芯片测试结果 ···············································································49 5.2.1 相位噪声测试结果 ·····························································49 5.2.2 正交相位精度测试 ·····························································55 5.2.3 功耗估计············································································59 5.2.4 摆幅测试············································································59 5.2.5 自激振荡频率测试 ·····························································60 5.2.6 工作频率范围测试 ·····························································60 第六章 总结和展望 ···················································································62 6.1 工作总结 ······················································································62 6.2 未来展望 ······················································································62 参考文献 ···································································································63 致谢···········································································································65 II
摘要 在无线通信应用中，频率综合器为射频收发机提供高精度的本振信号。分 频器是频率综合器中一个非常关键的模块。它关系着频率综合器能够实现的最 高速度和能够实现的工作频率范围。在数字电视调谐器等多标准应用中，可以 用分频器扩展频率综合器的频率范围，同时产生正交信号。本论文研究的主要 内容是分频器在频率综合器中的应用，并重点设计了一个宽频率范围的正交分 频器。 论文首先介绍了频率综合器的理论知识，研究了分频器在其中的应用，全 面总结和分析了各种分频器的结构和工作原理，比较了它们的优缺点。 其次，全面分析了Pulse-Swallow型多模可编程分频器。提出了异步4/4.5 双模预分频器结构，具有较小的品体管数目，能够降低功耗和节省面积。提出 种新型的S计数器结构，可以很好的与检测“2”结束状态的P计数器配合， 实现较高的速度。 再次，针对数字电视调谐器应用，利用SMIC0.18um工艺设计了一款正 交分频器，能够实现50~860MHz的正交信号。通过对分频器逻辑结构的改进， 减少了接收机所需要的混频器个数，从而节省芯片面积和减小功耗。 最后，给出了正交分频器的测试结果。芯片核心部分的面积为 390um×350μm,消耗的最大电流为6mA。测试表明，该分频器正确实现了分 频功能，性能指标达到了设计要求。当输出750MHz信号时，测得的正交相位 精度是1.14度。与频率综合器的级联测试表明，每经过一次除2，相位噪声性 能提高大约6dB。 关键词：频率综合器，分频器，4/4.5预分频器，可编程分频器，正交信号 中图分类号：TN432 本论文工作受到国家自然科学基金资助（项目编号：60876019） W
摘要 在无线通信应用中，频率综合器为射频收发机提供高精度的本振信号。分 频器是频率综合器中一个非常关键的模块。它关系着频率综合器能够实现的最 高速度和能够实现的工作频率范围。在数字电视调谐器等多标准应用中，可以 用分频器扩展频率综合器的频率范围，同时产生正交信号。本论文研究的主要 内容是分频器在频率综合器中的应用，并重点设计了一个宽频率范围的正交分 频器。 论文首先介绍了频率综合器的理论知识，研究了分频器在其中的应用，全 面总结和分析了各种分频器的结构和工作原理，比较了它们的优缺点。 其次，全面分析了 Pulse-Swallow 型多模可编程分频器。提出了异步 4/4.5 双模预分频器结构，具有较小的晶体管数目，能够降低功耗和节省面积。提出 一种新型的 S 计数器结构，可以很好的与检测“2”结束状态的 P 计数器配合， 实现较高的速度。 再次，针对数字电视调谐器应用，利用 SMIC 0.18μm 工艺设计了一款正 交分频器，能够实现 50~860MHz 的正交信号。通过对分频器逻辑结构的改进， 减少了接收机所需要的混频器个数，从而节省芯片面积和减小功耗。 最后，给出了正交分频器的测试结果。芯片核心部分的面积为 390μm×350μm，消耗的最大电流为 6mA。测试表明，该分频器正确实现了分 频功能，性能指标达到了设计要求。当输出 750MHz 信号时，测得的正交相位 精度是 1.14 度。与频率综合器的级联测试表明，每经过一次除 2，相位噪声性 能提高大约 6dB。 关键词：频率综合器，分频器，4/4.5 预分频器，可编程分频器，正交信号 中图分类号：TN432 本论文工作受到国家自然科学基金资助(项目编号：60876019) III
Abstract In wireless communication applications,frequency synthesizer is used to generalize high presise LO signals.In phase locked loop(PLL)-based frequency synthesizers,the frequency divider is one of the most important building blocks.It determines the highest speed and the frequency range of the frequency synthesizer.In multi-standard applications,such as the DTV-Tuner,divider may be used to extend the frequency range of the frequency synthesizer,or to generate the quadrature(1/Q)signal.The main focus of this thesis is the research of the applications of divider in frequency synthesizers,and the silicon verification of a quadrature divider with wide frequency range is realized. Firstly,this thesis summarizes a basic knowledge about frequency synthesizers,then focus on the application of frequency divider in frequency synthesizer.A comprehensive summary and comarisions of several main kinds of dividers are presented,including their structures and operating principles,and both the advantages and disadvantages in performance. Secondly,a detailed analysis of Pulse-Swallow Counter based multi-modulus programmable frequency divider is presented.The thesis presents a new structure of asynchronous 4/4.5 dual-modulus prescaler,the reduced number of transistors results in the reduction of power consumption and the chip area.A new structure of the Swallow Counter is proposed,which works well with the Program Counter which chooses"2"as the end-of-count state,thus the multi-modulus programmable frequency divider can operate at higher speed. Thirdly,a quadrature divider is realized in SMIC 0.18um technology,which can generalize the quadrature signal of 50~860MHz for DTV-Tuners.Through the choice of the divider structure,the number of mixers used in the receiver can be reduced from 5 to 1,which reduces the chip area and the power consumption. Finally,the measurement results are given.The core area of the chip is 390umx350um,and the maximum current of the core circuit is 6mA.The measurement result shows that the divider can operate well,and the performance agrees well with the design requirement.The mismatch of I/Q IV
Abstract In wireless communication applications, frequency synthesizer is used to generalize high presise LO signals. In phase locked loop(PLL)-based frequency synthesizers, the frequency divider is one of the most important building blocks. It determines the highest speed and the frequency range of the frequency synthesizer. In multi-standard applications, such as the DTV-Tuner, divider may be used to extend the frequency range of the frequency synthesizer, or to generate the quadrature (I/Q) signal. The main focus of this thesis is the research of the applications of divider in frequency synthesizers, and the silicon verification of a quadrature divider with wide frequency range is realized. Firstly, this thesis summarizes a basic knowledge about frequency synthesizers, then focus on the application of frequency divider in frequency synthesizer. A comprehensive summary and comarisions of several main kinds of dividers are presented, including their structures and operating principles, and both the advantages and disadvantages in performance. Secondly, a detailed analysis of Pulse-Swallow Counter based multi-modulus programmable frequency divider is presented. The thesis presents a new structure of asynchronous 4/4.5 dual-modulus prescaler, the reduced number of transistors results in the reduction of power consumption and the chip area. A new structure of the Swallow Counter is proposed, which works well with the Program Counter which chooses “2” as the end-of-count state, thus the multi-modulus programmable frequency divider can operate at higher speed. Thirdly, a quadrature divider is realized in SMIC 0.18μm technology, which can generalize the quadrature signal of 50~860MHz for DTV-Tuners. Through the choice of the divider structure, the number of mixers used in the receiver can be reduced from 5 to 1, which reduces the chip area and the power consumption. Finally, the measurement results are given. The core area of the chip is 390μm×350μm, and the maximum current of the core circuit is 6mA. The measurement result shows that the divider can operate well, and the performance agrees well with the design requirement. The mismatch of I/Q IV