复旦大学：《微电子学与固体电子学》教学资源（学士士学位论文）静电放电保护电路的分析与设计

学校代码：10246 学号：06300720401 復旦大架 学士学位论文 静电放电保护电路的分析与设计 院 系： 微电子学系 专 业： 微电子学与固体电子学 姓 名： 张唯一 指导教师： 唐长文副教授 完成日期： 2010年6月22日

学校代码： 10246 学 号： 06300720401 学 士 学 位 论 文 静电放电保护电路的分析与设计 院 系： 微电子学系 专 业： 微电子学与固体电子学 姓 名： 张唯一 指 导 教 师： 唐长文 副教授 完 成 日 期： 2010 年 6 月 22 日

目录 摘要… Abstract… …2 第一章概述… …3 1.1研究动机… 3 1.2研究内容及贡献 3 1.3论文组织结构… 4 第二章静电放电的基本概念 …5 2.1静电放电的模式… 5 2.2静电放电的测试… 6 2.2.1静电放电的测试组合… 6 2.22静电放电的故障判定… 6 2.3静电保护电路的基本架构… …7 第三章静电放电保护电路的设计…1 3.1/O保护电路… 11 3.1.1栅极接地NM○S… 12 3.1.2栅极耦合NMOS… 13 3.1.3硅控整流器… .14 3.1.4互补式I/O保护电路 16 3.1.5噪声… …18 3.2电源钳位电路… … 19 3.2.1RC触发MOSFET ESD电源钳位… 19 3.2.2简化的RC触发MOSFET ESD电源钳位… 21 第四章系统的静电放电保护… 23 4.1电路设计… 23 4.2正常工作时的仿真结果… 23 4.3ESD时的仿真结果… 25 第五章总结与展望 35 5.1总结… 35 5.2未来展望 35 参考文献… …36 致谢… …37

目录 摘要··············································································································1 Abstract ·······································································································2 第一章 概述 ·······························································································3 1.1 研究动机 ························································································3 1.2 研究内容及贡献 ·············································································3 1.3 论文组织结构·················································································4 第二章 静电放电的基本概念 ······································································5 2.1 静电放电的模式 ·············································································5 2.2 静电放电的测试 ·············································································6 2.2.1 静电放电的测试组合····························································6 2.2.2 静电放电的故障判定····························································6 2.3 静电保护电路的基本架构 ·······························································7 第三章 静电放电保护电路的设计····························································· 11 3.1 I/O保护电路 ················································································· 11 3.1.1 栅极接地NMOS·································································12 3.1.2 栅极耦合NMOS·································································13 3.1.3 硅控整流器········································································14 3.1.4 互补式I/O保护电路····························································16 3.1.5 噪声···················································································18 3.2 电源钳位电路···············································································19 3.2.1 RC触发MOSFET ESD电源钳位········································19 3.2.2 简化的RC触发MOSFET ESD电源钳位 ·····························21 第四章 系统的静电放电保护 ····································································23 4.1 电路设计 ······················································································23 4.2 正常工作时的仿真结果·································································23 4.3 ESD时的仿真结果········································································25 第五章 总结与展望 ··················································································35 5.1 总结 ·····························································································35 5.2 未来展望 ······················································································35 参考文献 ····································································································36 致谢············································································································37 I

摘要 随着集成电路工艺的发展，对静电放电保护的要求越来越高。本文的主要 目的，就是要设计一个能覆盖整个芯片的ESD保护网络，然后以此为目标展开 理论探讨和电路实现的相关工作。 本文首先从静电放电的基本概念出发，分析了ESD设计需要考虑的因素， 以及如何测试，怎样才算通过测试，从而引出设计目标，提出一种设计的基本 架构。 然后，文章自上而下地，从基本架构出发，细化到模块、器件，一一进行 分析，分别设计出O保护电路以及电源钳位电路。 接着，文章针对一个二输入二输出的简单系统，设计了一个ESD保护网络， 最后给出仿真结果。我们能看到每种测试模式都有合适的路径释放大电流。 关键词：静电放电，ESD保护网络，VO保护电路，电源钳位电路

摘要 随着集成电路工艺的发展，对静电放电保护的要求越来越高。本文的主要 目的，就是要设计一个能覆盖整个芯片的 ESD 保护网络，然后以此为目标展开 理论探讨和电路实现的相关工作。 本文首先从静电放电的基本概念出发，分析了 ESD 设计需要考虑的因素， 以及如何测试，怎样才算通过测试，从而引出设计目标，提出一种设计的基本 架构。 然后，文章自上而下地，从基本架构出发，细化到模块、器件，一一进行 分析，分别设计出 I/O 保护电路以及电源钳位电路。 接着，文章针对一个二输入二输出的简单系统，设计了一个 ESD 保护网络， 最后给出仿真结果。我们能看到每种测试模式都有合适的路径释放大电流。 关键词：静电放电，ESD 保护网络，I/O 保护电路，电源钳位电路 1

Abstract With the development of Ic manufacturing technology,it becomes demanding to protect the circuit from electrostatic discharge.The main purpose of this paper is to design an ESD protect network,which can be applied to cover all the IC to avoid ESD overstress.Based on this purpose,a lot of work about theoretic research and circuit implement are carried out. Firstly,this paper focuses on the basic concept of electrostatic discharge, analyses the principles in ESD design.How to test and the standard to pass the test are discussed.According to the theory,we are led to the design object. Then we get a kind of base configuration. Secondly,we try to design ESD protect circuit from top to bottom.We begin with the base configuration,and then,module and device.1/O protect circuit and VDD-to-VSS ESD clamp circuit are presented in this paper. And then,an ESD protect network for a two-input two-output system is designed.We get the simulation result at last.All ESD test mode can meet demand. Key word:Electrostatic discharge,ESD protect network,l/O protect circuit,VDD-to-VSS ESD clamp circuit 2

Abstract With the development of IC manufacturing technology, it becomes demanding to protect the circuit from electrostatic discharge. The main purpose of this paper is to design an ESD protect network, which can be applied to cover all the IC to avoid ESD overstress. Based on this purpose, a lot of work about theoretic research and circuit implement are carried out. Firstly, this paper focuses on the basic concept of electrostatic discharge, analyses the principles in ESD design. How to test and the standard to pass the test are discussed. According to the theory, we are led to the design object. Then we get a kind of base configuration. Secondly, we try to design ESD protect circuit from top to bottom. We begin with the base configuration, and then, module and device. I/O protect circuit and VDD-to-VSS ESD clamp circuit are presented in this paper. And then, an ESD protect network for a two-input two-output system is designed. We get the simulation result at last. All ESD test mode can meet demand. Key word: Electrostatic discharge, ESD protect network, I/O protect circuit, VDD-to-VSS ESD clamp circuit 2

第一章 概述 1.1研究动机 静电放电(Electrostatic Discharge,ESD)会对电子器件或电子系统造成电性 过度应力(Electrical Overstress,.EOS)[1],这种破坏会使半导体器件或者计算机 系统等形成一种永久性的毁坏，是造成集成电路失效的主要原因之一。据统计， 将近40%的集成电路失效是由静电放电引起的2]。集成电路工艺发展到深亚微 米阶段，特征尺寸不断缩小，更薄的栅氧化层，更短的沟道长度，更浅的源漏， 使MOS管能承受的电流和电压越来越小。又比如广泛应用的LDD结构，在源 漏两端形成“尖端”，在ESD电压下容易产生“尖端放电”现象。先进的工艺 使集成电路的静电放电保护能力下降，但外界环境中产生的静电并未减少，因 此要进一步优化电路的抗ESD性能。除了加强在流片、封装、测试、存放、搬 运过程中对静电累积的控制外，必须在电路中加入能防患静电放电的装置。 我们可以在芯片中做这样的设计，在大电流或高电压事件发生时，建立可 选的电流环路或第二路径，使ESD电流避开对过压敏感的电路。该电流环路必 须对ESD事件做出响应，即有“开关”，同时具有低阻抗。我们的测试假设在 断电状态下进行，因而ESD事件本身起到了电流和电压源的作用3]。所以，设 计的总体思路是利用低压触发网络把电流从敏感电路转移到可选电流路径，即 ESD保护电路。 ESD保护电路的作用是增加整个电路的ESD鲁棒性，首要的设计目的是避 免系统中任何物理元件遭受ESD事件带来的永久的或潜在的功能性、可靠性、 质的损害3]。其必然结果是要保证任意两引脚间发生的ESD,都有适合的低阻 旁路将ESD电流绕开内部电路，引入接地端，并且钳位关键点的电压。同时， 保护电路还要有很好的稳定性，能在ESD发生时快速响应、完整吸收，而且在 芯片正常工作时不能对工作电路有影响。 1.2研究内容及贡献 本论文着重研究了静电放电保护电路，其主要内容首先包括静电放电的基 本概念，主要是测试组合模式；然后从系统级出发，分析了保护网络的架构： 3

第一章 概述 1.1 研究动机 静电放电(Electrostatic Discharge, ESD)会对电子器件或电子系统造成电性 过度应力(Electrical Overstress, EOS)[1]，这种破坏会使半导体器件或者计算机 系统等形成一种永久性的毁坏，是造成集成电路失效的主要原因之一。据统计， 将近 40%的集成电路失效是由静电放电引起的[2]。集成电路工艺发展到深亚微 米阶段，特征尺寸不断缩小，更薄的栅氧化层，更短的沟道长度，更浅的源漏， 使 MOS 管能承受的电流和电压越来越小。又比如广泛应用的 LDD 结构，在源 漏两端形成“尖端”，在 ESD 电压下容易产生“尖端放电”现象。先进的工艺 使集成电路的静电放电保护能力下降，但外界环境中产生的静电并未减少，因 此要进一步优化电路的抗 ESD 性能。除了加强在流片、封装、测试、存放、搬 运过程中对静电累积的控制外，必须在电路中加入能防患静电放电的装置。 我们可以在芯片中做这样的设计，在大电流或高电压事件发生时，建立可 选的电流环路或第二路径，使 ESD 电流避开对过压敏感的电路。该电流环路必 须对 ESD 事件做出响应，即有“开关”，同时具有低阻抗。我们的测试假设在 断电状态下进行，因而 ESD 事件本身起到了电流和电压源的作用[3]。所以，设 计的总体思路是利用低压触发网络把电流从敏感电路转移到可选电流路径，即 ESD 保护电路。 ESD 保护电路的作用是增加整个电路的 ESD 鲁棒性，首要的设计目的是避 免系统中任何物理元件遭受 ESD 事件带来的永久的或潜在的功能性、可靠性、 质的损害[3]。其必然结果是要保证任意两引脚间发生的 ESD，都有适合的低阻 旁路将 ESD 电流绕开内部电路，引入接地端，并且钳位关键点的电压。同时， 保护电路还要有很好的稳定性，能在 ESD 发生时快速响应、完整吸收，而且在 芯片正常工作时不能对工作电路有影响。 1.2 研究内容及贡献 本论文着重研究了静电放电保护电路，其主要内容首先包括静电放电的基 本概念，主要是测试组合模式；然后从系统级出发，分析了保护网络的架构； 3