电子科技大学：《集成电路可测性设计 VLSIDesign》课程教学资源（课件讲稿）第11章 存储器测试

●0 ● 最常用的存储器 ●● ●●● ●●⊙@ RAMs:Random Access Memories Dynamic Random Acess Memory (DRAM) Highest possible density ● Slow access time (typically 20ns) ● Information stored as charge on capacitor and should be refreshed Static Random Acess Memory (SRAM) Fastest (typically 2ns) Information stored in cross coupled latches 2021/8/18 集成电路可测性设计 12

2021/8/18 集成电路可测性设计 12 最常用的存储器 RAMs: Random Access Memories  Dynamic Random Acess Memory (DRAM)  Highest possible density  Slow access time (typically 20ns)  Information stored as charge on capacitor and should be refreshed  Static Random Acess Memory (SRAM)  Fastest (typically 2ns)  Information stored in cross coupled latches

● 存储器测试 ●● ●●●● ●●●● ● Memory testing has to prove that the circuits under test behave as designed,it consists of: Parametric tests which concern voltage/current levels and delays on the lO pins of the chip Functional testing including dynamic testing 2021/8/18 集成电路可测性设计 13

2021/8/18 集成电路可测性设计 13 存储器测试  Memory testing has to prove that the circuits under test behave as designed, it consists of:  Parametric tests which concern voltage/current levels and delays on the IO pins of the chip  Functional testing including dynamic testing

● 参数（电气)测试 ●●0 ●● ●●● AC Parametric testing DC Parametric testing ●Rise and fall time Contact test Setup and hold time ●Power consumption ●Leakage test ●Delay test Threshold test ●Speed test Output drive current test ·Ippo testing(CMOS Output short current test memories only) Zero defect approach Use to detect some defects not handle by functional testing 2021/8/18 集成电路可测性设计 14

2021/8/18 集成电路可测性设计 14 参数（电气）测试  DC Parametric testing  Contact test  Power consumption  Leakage test  Threshold test  Output drive current test  Output short current test  AC Parametric testing  Rise and fall time  Setup and hold time  Delay test  Speed test  IDDQ testing (CMOS memories only)  Zero defect approach  Use to detect some defects not handle by functional testing

●●● ●●●● ●●●● 特征测试 ●●●● 6- 7 8- 9 10 Vdd 2.2 2.6 3.0 3.4 Shmoo图：Vdd-rp曲线 2021/8/18 集成电路可测性设计 15

2021/8/18 集成电路可测性设计 15 特征测试 6 7 8 9 10 2.2 2.6 3.0 3.4 Vdd p Shmoo图：Vdd-τp曲线

●● ●● ●●●● ●●0● ●●● 11.2存储器失效机理和故障模型 2021/8/18 集成电路可测性设计 16

2021/8/18 集成电路可测性设计 16 11.2 存储器失效机理和故障模型