复旦大学：《集成电路工程》教学资源（硕士士学位论文）分数分频频率综合器中噪声折叠问题的研究与电路设计

学校代码：10246 学号：11210720120 復大架 硕士学位论文 (专业学位) 分数分频频率综合器中噪声折叠问题的 研究与电路设计 院 系： 信息科学与工程学院 专 业： 集成电路工程 姓 名： 刘杰 指导教师： 唐长文副教授 完成日期： 2013年5月1日

学校代码：10246 学 号：11210720120 硕 士 学 位 论 文 (专业学位) 分数分频频率综合器中噪声折叠问题的 研究与电路设计 院 系： 信息科学与工程学院 专 业： 集成电路工程 姓 名： 刘 杰 指 导 教 师： 唐长文 副教授 完 成 日 期： 2013 年 5 月 1 日

目录 图目录… Ⅲ 表目录… …V 摘要… VII Abstract… Vi 第一章绪论… VIl 1.1研究背景… …1 1.2论文主要贡献… 2 1.3论文的研究内容和组织结构 2 第二章锁相环型频率综合器概述…。 5 2.1引言 …5 2.2整数分频频率综合器的基本结构 5 2.3整数分频频率综合器的基本结构… 6 2.3.1累加器型分数分频频率综合器…6 2.3.2∑△分数分频频率综合器… …8 2.4重要参数… …10 2.4.1杂散和相位噪声的定义 …10 2.4.2相位噪声模型… 12 2.4.3参考杂散… …15 2.4.4分数杂散 21 2.5本章小结 … 24 第三章分数分频频率综合器非线性分析… …25 3.1引言 25 3.2∑△分数分频频率综合器的基本结构及噪声模型 …25 3.2.1基本结构…。 25 3.2.2量化噪声与Σ△调制器结构… 26 3.2.3非线性条件下的噪声模型 29 3.3本章小结 37 第四章电路设计… 39 4.1引言… 39 4.2线性鉴频鉴相器电路设计 39 4.2.1鉴频鉴相器和电荷泵的传输特性…40

I 目录 图目录····························································································III 表目录·····························································································V 摘要······························································································VII Abstract ······················································································VIII 第一章 绪论 ···················································································VII 1.1 研究背景··············································································1 1.2 论文主要贡献········································································2 1.3 论文的研究内容和组织结构······················································2 第二章 锁相环型频率综合器概述··························································5 2.1 引言····················································································5 2.2 整数分频频率综合器的基本结构················································5 2.3 整数分频频率综合器的基本结构················································6 2.3.1 累加器型分数分频频率综合器 ··········································6 2.3.2 ΣΔ 分数分频频率综合器 ··················································8 2.4 重要参数·············································································10 2.4.1 杂散和相位噪声的定义 ··················································10 2.4.2 相位噪声模型 ······························································12 2.4.3 参考杂散 ····································································15 2.4.4 分数杂散 ····································································21 2.5 本章小结·············································································24 第三章 分数分频频率综合器非线性分析················································25 3.1 引言···················································································25 3.2 ΣΔ 分数分频频率综合器的基本结构及噪声模型 ···························25 3.2.1 基本结构 ····································································25 3.2.2 量化噪声与 ΣΔ 调制器结构·············································26 3.2.3 非线性条件下的噪声模型 ···············································29 3.3 本章小结·············································································37 第四章 电路设计··············································································39 4.1 引言···················································································39 4.2 线性鉴频鉴相器电路设计························································39 4.2.1 鉴频鉴相器和电荷泵的传输特性······································40

4.2.2现有的线性化技术介绍 …41 4.2.3线性鉴频鉴相器电路设计…43 4.3分频器链设计…47 4.4分数杂散的设计考虑 49 4.5本章小结… 49 第五章芯片设计及芯片测试… 51 5.1引言… …51 5.2芯片实现… 51 5.3测试结果…。 53 5.3.1频率调谐范围最小分辨率及功耗测试结果 53 5.3.2相位噪声测试结果 53 5.3.3分数杂散测试结果… 55 5.3.4环路带宽和积分相位误差测试结果…56 5.3.5分频器链性能测试结果 57 5.3.6锁定时间测试结果 59 5.4本章小结 60 第六章总结与展望… 61 6.1工作总结… 61 6.2未来展望… 62 参考文献… 63 致谢… 67

II 4.2.2 现有的线性化技术介绍 ··················································41 4.2.3 线性鉴频鉴相器电路设计 ···············································43 4.3 分频器链设计·······································································47 4.4 分数杂散的设计考虑······························································49 4.5 本章小结·············································································49 第五章 芯片设计及芯片测试·······························································51 5.1 引言···················································································51 5.2 芯片实现·············································································51 5.3 测试结果·············································································53 5.3.1 频率调谐范围最小分辨率及功耗测试结果··························53 5.3.2 相位噪声测试结果 ························································53 5.3.3 分数杂散测试结果 ························································55 5.3.4 环路带宽和积分相位误差测试结果···································56 5.3.5 分频器链性能测试结果 ··················································57 5.3.6 锁定时间测试结果 ························································59 5.4 本章小结·············································································60 第六章 总结与展望···········································································61 6.1 工作总结·············································································61 6.2 未来展望·············································································62 参考文献·························································································63 致谢·······························································································67

图目录 图2-1整数分频频率综合器结构框图 .5 图2-2基于累加器的分数分频频率综合器结构框图.. .7 图2-3分频比在4.25时分数分频频率综合器中的量化噪声.... .7 图2-4∑△分数分频综合器结构框图.… .8 图2-5∑△型频率综合器噪声特性 .9 图2-6正弦信号的频谱 .10 图2-7毛刺和相位噪声. .12 图2-8整数分频频率综合器的S域模型.. ..13 图2-9整数分频频率综合器相位噪声模型. .13 图2-10各模块自身噪声、噪声传递函数和等效输出噪声 .15 图2-11理想情况下整数分频综合器工作状态.16 图2-12泄漏电流引起参考杂散的机制. 18 图2-13控制信号up和dn的偏差对参考杂散的影响 .19 图2-14延迟平衡的鉴频鉴相器...… ..19 图2-15电荷泵失配对参考杂散的影响.… .20 图2-16电荷共享对参考杂散的影响.… .21 图2-17产生分数杂散的三种耦合机制 22 图2-18周期矩形波信号. .23 图3-1基于∑△调制器的分数分频频率综合器的结构 26 图3-2一阶∑△调制器结构及线性化z域模型 27 图3-3分数分频频率综合器噪声模型 28 图3-4分数分频器参考时钟和分频器时钟工作状态.… 29 图3-5电荷泵模型 31 图3-6电荷泵数学模型. 32 图3-7存在非线性情况下分数分频频率综合器噪声模型 33 图3-8存在非线性情况下量化噪声对输出噪声的贡献 .36 图4-1PFD/CP结构及理想CP情况下传输特性... 40 图4-2PFD/CP的非线性情况下的传输曲线 40 图4-3 dc Current Offset线性化技术........... ..41 图4-4增加延时来消除非线性的电路结构及工作时序图 42 图4-5基于采样开关的环路滤波器… 43

III 图目录 图 2-1 整数分频频率综合器结构框图..............................................................5 图 2-2 基于累加器的分数分频频率综合器结构框图.........................................7 图 2-3 分频比在 4.25 时分数分频频率综合器中的量化噪声 ............................7 图 2-4 ΣΔ 分数分频综合器结构框图 ................................................................8 图 2-5 ΣΔ 型频率综合器噪声特性....................................................................9 图 2-6 正弦信号的频谱 .................................................................................10 图 2-7 毛刺和相位噪声 .................................................................................12 图 2-8 整数分频频率综合器的 s 域模型 ........................................................13 图 2-9 整数分频频率综合器相位噪声模型.....................................................13 图 2-10 各模块自身噪声、噪声传递函数和等效输出噪声 .............................15 图 2-11 理想情况下整数分频综合器工作状态................................................16 图 2-12 泄漏电流引起参考杂散的机制..........................................................18 图 2-13 控制信号 up 和 dn 的偏差对参考杂散的影响....................................19 图 2-14 延迟平衡的鉴频鉴相器.....................................................................19 图 2-15 电荷泵失配对参考杂散的影响..........................................................20 图 2-16 电荷共享对参考杂散的影响..............................................................21 图 2-17 产生分数杂散的三种耦合机制..........................................................22 图 2-18 周期矩形波信号 ...............................................................................23 图 3-1 基于 ΣΔ 调制器的分数分频频率综合器的结构....................................26 图 3-2 一阶 ΣΔ 调制器结构及线性化 z 域模型 ..............................................27 图 3-3 分数分频频率综合器噪声模型............................................................28 图 3-4 分数分频器参考时钟和分频器时钟工作状态.......................................29 图 3-5 电荷泵模型.........................................................................................31 图 3-6 电荷泵数学模型 .................................................................................32 图 3-7 存在非线性情况下分数分频频率综合器噪声模型 ...............................33 图 3-8 存在非线性情况下量化噪声对输出噪声的贡献...................................36 图 4-1 PFD/CP 结构及理想 CP 情况下传输特性............................................40 图 4-2 PFD/CP 的非线性情况下的传输曲线 ..................................................40 图 4-3 dc Current Offset 线性化技术 .............................................................41 图 4-4 增加延时来消除非线性的电路结构及工作时序图 ...............................42 图 4-5 基于采样开关的环路滤波器................................................................43

图4-6改进的线性PFD电路.... .44 图4-7线性PFD在锁定状态下的工作时序图... .44 图4-8百k宽度的Monto Carl0仿真结果... .45 图4-9增加选择器的线性PD电路及其时序图 ..46 图4-10线性PFD的Spur特性. .46 图4-11分频器链电路设计及频率对应关系. ..47 图4-12二分频器电路.… 48 图5-1分数分频宽带频率综合器芯片照片… 52 图5-2载波频率为1GHz时综合器输出相位噪声测试曲线. .53 图5-3线性PFD模式下和传统模式下相位噪声比较… .54 图5-4参考杂散性能的测试.… .54 图5-5输出频率1.00000827GHz时分数Spur的测试结果 ..55 图5-6不同频率下的分数Spur测试结果… .56 图5-7环路带宽和积分相位误差测试结果.56 图5-8分频器链不同分频比下的输出信号相位噪声测试 ..57 图5-9分频器链不同分频比下的输出信号相位积分相位误差测试 ..58 图5-10分频器链输出/Q信号的镜像抑制测试..... .58 图5-11锁定时间测试结果… .59 IV

IV 图 4-6 改进的线性 PFD 电路.........................................................................44 图 4-7 线性 PFD 在锁定状态下的工作时序图 ...............................................44 图 4-8 δk 宽度的 Monto Carlo 仿真结果 .........................................................45 图 4-9 增加选择器的线性 PFD 电路及其时序图............................................46 图 4-10 线性 PFD 的 Spur 特性 ....................................................................46 图 4-11 分频器链电路设计及频率对应关系 ...................................................47 图 4-12 二分频器电路...................................................................................48 图 5-1 分数分频宽带频率综合器芯片照片.....................................................52 图 5-2 载波频率为 1GHz 时综合器输出相位噪声测试曲线............................53 图 5-3 线性 PFD 模式下和传统模式下相位噪声比较.....................................54 图 5-4 参考杂散性能的测试 ..........................................................................54 图 5-5 输出频率 1.00000827GHz 时分数 Spur 的测试结果 ..........................55 图 5-6 不同频率下的分数 Spur 测试结果 ......................................................56 图 5-7 环路带宽和积分相位误差测试结果......................................................56 图 5-8 分频器链不同分频比下的输出信号相位噪声测试 ...............................57 图 5-9 分频器链不同分频比下的输出信号相位积分相位误差测试 .................58 图 5-10 分频器链输出 I/Q 信号的镜像抑制测试 ............................................58 图 5-11 锁定时间测试结果 ............................................................................59