ON MT9P031:1/2.5-Inch 5 Mp Digital Imag ge sensor Output Data Timing Frame Rates at Common Resolutions am ohCgstsetwng5toachie ngemaicalamanrions sampnng ena disabled. Table10: Standard Resolutions ub- Column_s Resolution (R0x09) 592x】 14 2591 1943 <194 5360CA3 N/A 30A7 1G35 Z130 1600x1200xA31 N/A 1599 1199 1199 1280x10245XGA42 N/A 1279 1023 <1023 63 N/A 1023 767 1024x768XGA 63 skipping 2047 1535 <767 47 binning 2047 1535 90 N/A 799 599 800×600SVGA 90 skipping 1599 1199 <599 62 binning 1599 1199 N/A 63 47 640x480VGA (479 2559 Wide Screen(16:9)Resolutions Resolution (R0x03 ☏ 31 N/A 1919 1079 <1079 N/A 1280×720HDTV 27 719 719 259 1439 Notes. 1.It isassumed that the minimum horizontal blanking and the minimum vertical blanking conditions are met,and that all other registers are set to default value Mr931.D5R1515W 6
MT9P031_DS Rev. J 5/15 EN 16 ©Semiconductor Components Industries, LLC,2015. MT9P031: 1/2.5-Inch 5 Mp Digital Image Sensor Output Data Timing Frame Rates at Common Resolutions Table 10 and Table 11 show examples of register settings to achieve common resolutions and their frame rates. Frame rates are shown both with subsampling enabled and disabled. Notes: 1. It is assumed that the minimum horizontal blanking and the minimum vertical blanking conditions are met, and that all other registers are set to default values. Table 10: Standard Resolutions Resolution Frame Rate Subsampling Mode Column_S ize (R0x04) Row_ Size (R0x03) Shutter_ Width_ Lower (R0x09) Row_ Bin (R0x22 [5:4]) Row_ Skip (R0x22 [2:0]) Column_Bin (R0x23 [5:4]) Column_Skip (R0x23 [2:0]) 2592 x 1944 (Full Resolution) 14 N/A 2591 1943 <1943 0 0 0 0 2048 x 1536 QXGA 21 N/A 2047 1535 <1535 0 0 0 0 1600 x 1200 UXGA 31 N/A 1599 1199 <1199 0 0 0 0 1280 x 1024 SXGA 42 N/A 1279 1023 <1023 0 0 0 0 1024 x 768 XGA 63 N/A 1023 767 <767 00 0 0 63 skipping 2047 1535 0 1 0 1 47 binning 2047 1535 1 1 1 1 800 x 600 SVGA 90 N/A 799 599 <599 00 0 0 90 skipping 1599 1199 0 1 0 1 65 binning 1599 1199 1 1 1 1 640 x 480 VGA 123 N/A 639 479 <479 00 0 0 123 skipping 2559 1919 0 3 0 3 53 binning 2559 1919 3 3 3 3 Table 11: Wide Screen (16:9) Resolutions Resolution Frame Rate Subsampling Mode Column_Si ze (R0x04) Row_ Size (R0x03) Shutter_ Width_ Lower (R0x09) Row_ Bin (R0x22 [5:4]) Row_ Skip (R0x22 [2:0]) Column_Bi n (R0x23 [5:4]) Column_Ski p (R0x23 [2:0]) 1920 x 1080 HDTV 31 N/A 1919 1079 <1079 0 0 0 0 1280 x 720 HDTV 60 N/A 1279 719 <719 0 0 0 0 60 skipping 2559 1439 <719 0 1 0 1 45 binning 2559 1439 <719 1 1 1 1
ON MT9P31:1/25-Inch5Mp Serial Bus Description al interface slave a s contro d by chip by a 1.5k resistor.Either the slave or master device can pull the SDATA line LOW- the serial interface protocol determines which device is allowed to pull the SDATA line down at any given time Protocol The two-wire serial defines several different transmission codes,as follows: 1.astart bit 2.the slave device 8-bit address 3.an(a no)acknowledge bit 4.an 8-bit message 5.a stop bit Sequence ding a start bit. READ r a WRITE.whe s a WRITE and a“1" indicates a READ.The slave device acknowledges its address by sending an acknowledge bit back to the master. eteeiaa心RIethmiterthermncrohe&g f the tis a WRITE th he &.hit which a register address has been received.The master then transfers the data 8 bits at a time with the slave sending an acknowledge bit after each 8 bits.The MT9P031 uses 16-bit data for interal registers.thusr equing two oit transters to write to on e register sending a start or stop bit. typical READ ed as s.First the ster sends the write-n register data 8 bits at a time.The master sends an acknowledge bit after each 8-bit trans en th e master sends edge Bus Idle State The bus is idle when both the data and clock lines are HIGH.Control of the bus is initi- ated with a start bit,and the bus is released with a stop bit.Only the master can generate the start and stop bits Start Bit The start bit is defined as a HIGH-to-LOW transition of the data line while the clock line isHIGH
MT9P031_DS Rev. J 5/15 EN 17 ©Semiconductor Components Industries, LLC,2015. MT9P031: 1/2.5-Inch 5 Mp Digital Image Sensor Serial Bus Description Serial Bus Description Registers are written to and read from the MT9P031 through the two-wire serial interface bus. The MT9P031 is a serial interface slave and is controlled by the serial clock (SCLK), which is driven by the serial interface master. Data is transferred into and out of the MT9P031 through the serial data (SDATA) line. The SDATA line is pulled up to VDD_IO offchip by a 1.5k resistor. Either the slave or master device can pull the SDATA line LOW— the serial interface protocol determines which device is allowed to pull the SDATA line down at any given time. Protocol The two-wire serial defines several different transmission codes, as follows: 1. a start bit 2. the slave device 8-bit address 3. an (a no) acknowledge bit 4. an 8-bit message 5. a stop bit Sequence A typical READ or WRITE sequence begins by the master sending a start bit. After the start bit, the master sends the slave device's 8-bit address. The last bit of the address determines if the request is a READ or a WRITE, where a “0” indicates a WRITE and a “1” indicates a READ. The slave device acknowledges its address by sending an acknowledge bit back to the master. If the request is a WRITE, the master then transfers the 8-bit register address to which a WRITE should take place. The slave sends an acknowledge bit to indicate that the register address has been received. The master then transfers the data 8 bits at a time, with the slave sending an acknowledge bit after each 8 bits. The MT9P031 uses 16-bit data for its internal registers, thus requiring two 8-bit transfers to write to one register. After 16 bits are transferred, the register address is automatically incremented, so that the next 16 bits are written to the next register address. The master stops writing by sending a start or stop bit. A typical READ sequence is executed as follows. First the master sends the write-mode slave address and 8-bit register address, just as in the WRITE request. The master then sends a start bit and the read-mode slave address. The master then clocks out the register data 8 bits at a time. The master sends an acknowledge bit after each 8-bit transfer. The register address is automatically-incremented after every 16 bits is transferred. The data transfer is stopped when the master sends a no-acknowledge bit. Bus Idle State The bus is idle when both the data and clock lines are HIGH. Control of the bus is initiated with a start bit, and the bus is released with a stop bit. Only the master can generate the start and stop bits. Start Bit The start bit is defined as a HIGH-to-LOW transition of the data line while the clock line is HIGH