ON /2-InchMp General Description An on-chip analog-to-digital converter (ADC)provides 12 bits per pixel.FRAME_VALID The MT9P031produces extraordinarily clear,sharp digital pictures,and its ability to cameras Functional Overview l clocks from a single master input clock running between 6 and 27 MHz The maximum pixel rate is96 Mp/s,corresponding to a clock rate of96 MHz.Figure 1 illustrates a block diagram of the sensor. Figure 1:Block Diagram GGER Pixel Array nierl 2752H×2004V 网 Analog Signal Chain Data Path STRORE User interaction with the sensor is through the two-wire serial bus,which communi- cates with the array control,analog signal chain,and digital signal chain.The core of the sensor isa 5Mp active-pixel array.The tming e incident light.The exposure is controlled by varying the time interval between reset and readout. que 1-au)and th nced through an analog hen through a AD through a digital processing signal chain (which provides further data path corre and applies digital gain).The pixel data are output at a rate ofup toMp/s,in addition to frame and line synchronization signals. MT3P_0cs/N 6
MT9P031_DS Rev. J 5/15 EN 6 ©Semiconductor Components Industries, LLC,2015. MT9P031: 1/2.5-Inch 5 Mp Digital Image Sensor General Description General Description The MT9P031 sensor can be operated in its default mode or programmed by the user for frame size, exposure, gain setting, and other parameters. The default mode outputs a full resolution image at 14 frames per second (fps). An on-chip analog-to-digital converter (ADC) provides 12 bits per pixel. FRAME_VALID (FV) and LINE_VALID (LV) signals are output on dedicated pins, along with a pixel clock that is synchronous with valid data. The MT9P031produces extraordinarily clear, sharp digital pictures, and its ability to capture both continuous video and single frames makes it the perfect choice for a wide range of consumer and industrial applications, including cell phones, digital still cameras, digital video cameras, and PC cameras. Functional Overview The MT9P031 is a progressive-scan sensor that generates a stream of pixel data at a constant frame rate. It uses an on-chip, phase-locked loop (PLL) to generate all internal clocks from a single master input clock running between 6 and 27 MHz. The maximum pixel rate is 96 Mp/s, corresponding to a clock rate of 96 MHz. Figure 1 illustrates a block diagram of the sensor. Figure 1: Block Diagram User interaction with the sensor is through the two-wire serial bus, which communicates with the array control, analog signal chain, and digital signal chain. The core of the sensor is a 5Mp active-pixel array. The timing and control circuitry sequences through the rows of the array, resetting and then reading each row in turn. In the time interval between resetting a row and reading that row, the pixels in the row integrate incident light. The exposure is controlled by varying the time interval between reset and readout. Once a row has been read, the data from the columns is sequenced through an analog signal chain (providing offset correction and gain), and then through an ADC. The output from the ADC is a 12-bit value for each pixel in the array. The ADC output passes through a digital processing signal chain (which provides further data path corrections and applies digital gain). The pixel data are output at a rate of up to 96 Mp/s, in addition to frame and line synchronization signals. Pixel Array 2752H x 2004V SCLK SDATA SADDR PIXCLK DOUT[11:0] LV FV STROBE Serial Interface Analog Signal Chain Data Path TRIGGER EXTCLK RESET_BAR STANDBY_BAR OE Array Control Output
ON Ser ON MT9P031:1/2.5-Inch 5 Mp Digital In Figure 2: Typical Configuration(Connection) 2 SADD STANDEY BAR 1 onte rolle Notes:1.A resistorvalue of 15kis re 3.All DGND ust betied toether asmust al AGND pinsal Vpins,ad all VD pins. Figure 3: 48-Pin iLCC 10 x 10 Package Pinout Diagram (Top View) FRAME VALID LINE_VALID STROBE ▣DOUTE DGND ▣VDD_IO VDD IO SADDR ▣D0UT3 STANDBY BAR ▣D0m2 TRIGGER DoUt1 RESET BAR EXTCLK 8
MT9P031_DS Rev. J 5/15 EN 7 ©Semiconductor Components Industries, LLC,2015. MT9P031: 1/2.5-Inch 5 Mp Digital Image Sensor Functional Overview Figure 2: Typical Configuration (Connection) Notes: 1. A resistor value of 1.5k is recommended, but may be greater for slower two-wire speed. 2. All power supplies should be adequately decoupled. 3. All DGND pins must be tied together, as must all AGND pins, all VDD_IO pins, and all VDD pins. Figure 3: 48-Pin iLCC 10 x 10 Package Pinout Diagram (Top View) DOUT[11:0] PIXCLK FV LV STROBE SADDR RESET_BAR STANDBY_BAR SCLK SDATA TRIGGER VDD_IO AGND3 TEST 1.5kW1 1.5kW1 VDD_IO2,3 VDD VDD2,3 1μF 10k W RSVD DGND3 VDD_PLL VAA_PIX VAA VAA2,3 OE To From controller controller Master clock EXTCLK 6 48 47 46 45 5 4 3 2 1 44 43 19 20 21 22 23 24 25 26 27 28 29 30 7 8 9 10 11 12 13 14 15 16 17 18 42 41 40 39 38 37 36 35 34 33 32 31 FRAME_VALID LINE_VALID STROBE DGND VDD_IO VDD SADDR STANDBY_BAR TRIGGER RESET_BAR OE NC DOUT8 DOUT7 DOUT6 VDD_IO DOUT5 DOUT4 DOUT3 DOUT2 DOUT1 DOUT0 PIXCLK EXTCLK NC TEST TEST AGND VAA VAA VDD_PLL DGND NC NC NC NC RSVD SDATA SCLK TEST AGND VAA_PIX VAA_PIX VDD DGND DOUT11 DOUT10 DOUT9
Mw9Po311/251hcn5MDeaelDgaeSnmat Table3: Pin Description Name Description RESET_BAR Input pperation with all configuration registers set to factory defaults. HIGH,it resumes norm EXTCIK Input xternal input clock. SCIK Input erial clock pull to Voo lowith a 1 5ko resistor OE Input STANDBY_BAR Input TRIGGER Input in snapshot modesandto SADDR Input erial add to device ID(BA)When LOW,it SDATA 1/o erial data.Pull to VoD O with a 1.5k resistor. PIXCLK Output el clock.The DoUT,FV,LV,and STROBE outputs should be captured on the falling edge of this signal. DoUT[11:0] Output Pixel data.Pixel data is 12-bit.MSB(DoUT11)through LSB(DoUTO)of each pixel,to be captured on the falling edge of PIXCL FRAME_VALID Output oWiUalgemealtlGndlrim8actepiesandhoromtalblankingofeachfameand Output lid Drive ve pi els of each line and LOW during bla ng periods. Output n HIGH wher ll pixels are exposing in snapshot modes Supply Digital supply voltage.Nominally 18V Supply Osupply voltage.Nominally 1.8 or 2.8V. DGND Supply Digital ground. VAA Supply Analog supply voltage.Nominally 2.8V. VAA PIX Supply Pixel supply voltage.Nominally 2.8V,connected externally to VAA. AGND Supply Analog ground. VDD_PLL Supply PLLsupply voltage.Nominally 2.8V,connected externally to VAA. TEST Tie to AGND for normal device operation(factory use only). RSVD ie to dGND for normal device operation (factory use onlyi No connect. Pixel Data Format Pixel Array Structure eoeneakgeaagEgogegrerne addre Ttearpycensitsofa25e92.com9boateg2aaeeetedeb the de of daput e su0endedbYabb加5ndagego (a d to avoid edge effects when doing color processing to achieve a 2592x 1944 result image while the optically black column and rows can be used to monitor the black level. MTP00S EN
MT9P031_DS Rev. J 5/15 EN 8 ©Semiconductor Components Industries, LLC,2015. MT9P031: 1/2.5-Inch 5 Mp Digital Image Sensor Pixel Data Format Pixel Data Format Pixel Array Structure The MT9P031 pixel array consists of a 2752-column by 2004-row matrix of pixels addressed by column and row. The address (column 0, row 0) represents the upper-right corner of the entire array, looking at the sensor, as shown in Figure 4 on page 9. The array consists of a 2592-column by 1944-row active region in the center representing the default output image, surrounded by a boundary region (also active), surrounded by a border of dark pixels (see Table 4 and Table 5). The boundary region can be used to avoid edge effects when doing color processing to achieve a 2592 x 1944 result image, while the optically black column and rows can be used to monitor the black level. Table 3: Pin Description Name Type Description RESET_BAR Input When LOW, the MT9P031 asynchronously resets. When driven HIGH, it resumes normal operation with all configuration registers set to factory defaults. EXTCLK Input External input clock. SCLK Input Serial clock. Pull to VDD_IO with a 1.5k resistor. OE Input When HIGH, the PIXCLK, DOUT, FV, LV, and STROBE outputs enter a High-Z. When driven LOW, normal operation resumes. STANDBY_BAR Input Standby. When LOW, the chip enters a low-power standby mode. It resumes normal operation when the pin is driven HIGH. TRIGGER Input Snapshot trigger. Used to trigger one frame of output in snapshot modes, and to indicate the end of exposure in bulb exposure modes. SADDR Input Serial address. When HIGH, the MT9P031 responds to device ID (BA)H. When LOW, it responds to serial device ID (90)H. SDATA I/O Serial data. Pull to VDD_IO with a 1.5k resistor. PIXCLK Output Pixel clock. The DOUT, FV, LV, and STROBE outputs should be captured on the falling edge of this signal. DOUT[11:0] Output Pixel data. Pixel data is 12-bit. MSB (DOUT11) through LSB (DOUT0) of each pixel, to be captured on the falling edge of PIXCLK. FRAME_VALID Output Frame valid. Driven HIGH during active pixels and horizontal blanking of each frame and LOW during vertical blanking. LINE_VALID Output Line valid. Driven HIGH with active pixels of each line and LOW during blanking periods. STROBE Output Snapshot strobe. Driven HIGH when all pixels are exposing in snapshot modes. VDD Supply Digital supply voltage. Nominally 1.8V. VDD_IO Supply IO supply voltage. Nominally 1.8 or 2.8V. DGND Supply Digital ground. VAA Supply Analog supply voltage. Nominally 2.8V. VAA_PIX Supply Pixel supply voltage. Nominally 2.8V, connected externally to VAA. AGND Supply Analog ground. VDD_PLL Supply PLL supply voltage. Nominally 2.8V, connected externally to VAA. TEST — Tie to AGND for normal device operation (factory use only). RSVD — Tie to DGND for normal device operation (factory use only). NC — No connect
ON Se ON MT9P031:1/2.5-Inch 5 Mp Digital In ixe des ar 四he sooupand pivend由o the sme o filter,but they are treated as separate colors by the data path and analog signal chain. Table4: Pixel Type by Column Column Pixel Type 0-9 Dark(10) 105 16-2607 Active bo y(6 2608-2617 2618-2751 Dark (134) Table5: Pixel Type by Row Row Pixel Type -49 Dark(5o) Active boundary (4) ary (3) Dark Figure 4: Pixel Array Description 50 black row 49 134black colu mr 2592×1944 10 black columns active pixels 2751,2003 row 9
MT9P031_DS Rev. J 5/15 EN 9 ©Semiconductor Components Industries, LLC,2015. MT9P031: 1/2.5-Inch 5 Mp Digital Image Sensor Pixel Data Format Pixels are output in a Bayer pattern format consisting of four “colors”—GreenR, GreenB, Red, and Blue (Gr, Gb, R, B)—representing three filter colors. When no mirror modes are enabled, the first row output alternates between Gr and R pixels, and the second row output alternates between B and Gb pixels. The Gr and Gb pixels have the same color filter, but they are treated as separate colors by the data path and analog signal chain. Figure 4: Pixel Array Description Table 4: Pixel Type by Column Column Pixel Type 0–9 Dark (10) 10–15 Active boundary (6) 16–2607 Active image (2592) 2608–2617 Active boundary (10) 2618–2751 Dark (134) Table 5: Pixel Type by Row Row Pixel Type 0– 49 Dark (50) 50–53 Active boundary (4) 54–1997 Active image (1944) 1998–2001 Active boundary (3) 2002–2003 Dark (2) (2751, 2003) 10 black columns 2 black rows 50 black rows (0,0) 134 black columns Active Image 2592 x 1944 active pixels 4 (16,54) 10 6 4
ON MT9Po31:1/2.5hch5MpDeEIa8S8nmaL Figure 5: Pixel Color Pattern Detail(Top Right Corner) black pixels pixe (.50) @R R Gr R C面 B Cb B Cb B Cb B Gr R Gr R Gr R Gr B b Gr R Gr R Gr R Gr Default Readout Order By convention,the sensor core pixel array is shown with pixel (0,0)in the top right corner(see Figure 4).This reflects the actual layout of the array on the die.Also,the first pixel data read out of the sensor in default condition is that of pixel (16,54). When the rows and columns sequenced as shown in Figure 6 on page 10. Figure 6: Imaging a Scene Sensor (rear view) Order xel(O.0) MTP00S EN 6
MT9P031_DS Rev. J 5/15 EN 10 ©Semiconductor Components Industries, LLC,2015. MT9P031: 1/2.5-Inch 5 Mp Digital Image Sensor Pixel Data Format Figure 5: Pixel Color Pattern Detail (Top Right Corner) Default Readout Order By convention, the sensor core pixel array is shown with pixel (0,0) in the top right corner (see Figure 4). This reflects the actual layout of the array on the die. Also, the first pixel data read out of the sensor in default condition is that of pixel (16, 54). When the sensor is imaging, the active surface of the sensor faces the scene as shown in Figure 5. When the image is read out of the sensor, it is read one row at a time, with the rows and columns sequenced as shown in Figure 6 on page 10. Figure 6: Imaging a Scene FIrst clear pixel (10,50) black pixels column readout direction . . . . . . . row readout direction Gr B Gr B Gr B R Gb R Gb R Gb Gr B Gr B Gr B R Gb R Gb R Gb Gr B Gr B Gr B R Gb R Gb R Gb Gr B Gr B Gr B Lens Pixel (0,0) Row Readout Order Column Readout Order Scene Sensor (rear view)