复旦大学：《微电子学与固体电子学》教学资源（博士士学位论文）高精度、低功耗流水线型模数转换器的研究与设计

第一章前言 文献[50]采用了一种串联式双NMOS输入差分对的方法。这种方法较前一 种比起来，各级都采用了NMOS作为运放的输入管，从而可以提高电流的利用 效率，同时也通过双输入交替工作和复位至共模电压来解决了记忆效应等问题。 但是由于两对输入管是上下串联，需要接到各自不同的共模电压，因此在电路中 需要产生两组复位电平；同时，两个串联的输入管还会降低运放的输出摆幅，使 其难以应用于低功耗的套筒式运放：此外，当开关闭合时，其寄生电阻会降低运 放的增益和单位增益带宽。 上述几种方法以一定的功耗和电路复杂度为代价，在一定程度上改善了传统 运放共享结构中存在的影响电路精度的因素。因此，如何完全高效地解决记忆效 应、级间串扰、电荷注入和时钟馈通等问题仍然是需要进一步研究和解决的课题。 1.3论文研究的主要工作 本论文首先从降低系统整体功耗入手，采用了级间运放共享技术来减小运放 数量，再从减小运放功耗的角度选择了能效比最高的增益自举套筒式运放结构。 之后，本文详细分析了采用传统运放共享技术所存在的记忆效应、级间串扰通路 以及和运放共享开关引入的电荷注入和时钟馈通等问题，指出其降低了系统的精 度的原因。 其次，为了消除这些因素对系统精度的影响，提出一种新型适用于运放共享 的双输入开关内置余量增益放大电路(MDAC),有效地提高了电路的性能。同时 通过对开关内置的双输入MDAC电路的分析，提出采用双相交叠时钟来控制运 放共享开关，解决了采用传统非交叠时钟导致的大信号建立恶化等问题。优化了 宽摆幅运放偏置电路，使其与运放获得更好的匹配。 此外，本论文还分析了流水线模数转换器中各种非理想因素对系统的影响， 从真实电路中信号传递和量化的角度，建立了流水线模数转换器的Matlab模型， 并引入了诸如电容失配、噪声、运放单位增益带宽、运放压摆率、时钟抖动以及 比较器失调等绝大多数的非理想因素，从而指导电路设计，模型仿真与流片测试 结果相当契合。 本论文在SMIC0.18-m、1.8V电源电压、单层多晶硅六层金属的标准 CMOS工艺下，设计实现了一款分辨率为10bit采速率为80MSps的高精度、低 功耗流水线型模数转换器。在电路设计过程中，本论文也把许多相关的研究论文 作为设计时的参考51-68]。通过将芯片测试结果与国内外研究的对比，本设计中 的流水线模数转换器在近几年发表的文献中处于较高水平。 最后，为了进一步降低系统功耗，采用了使采样保持电路与第一级MDAC 共享运放的方法，设计了一款11bit的流水线模数转换器。由于采样保持电路和 第一级MDAC均对运放功耗有着最高的要求，因此这两者共享运放可以很大程 3

第一章 前言 3 文献[50]采用了一种串联式双 NMOS 输入差分对的方法。这种方法较前一 种比起来，各级都采用了 NMOS 作为运放的输入管，从而可以提高电流的利用 效率，同时也通过双输入交替工作和复位至共模电压来解决了记忆效应等问题。 但是由于两对输入管是上下串联，需要接到各自不同的共模电压，因此在电路中 需要产生两组复位电平；同时，两个串联的输入管还会降低运放的输出摆幅，使 其难以应用于低功耗的套筒式运放；此外，当开关闭合时，其寄生电阻会降低运 放的增益和单位增益带宽。 上述几种方法以一定的功耗和电路复杂度为代价，在一定程度上改善了传统 运放共享结构中存在的影响电路精度的因素。因此，如何完全高效地解决记忆效 应、级间串扰、电荷注入和时钟馈通等问题仍然是需要进一步研究和解决的课题。 1.3 论文研究的主要工作 本论文首先从降低系统整体功耗入手，采用了级间运放共享技术来减小运放 数量，再从减小运放功耗的角度选择了能效比最高的增益自举套筒式运放结构。 之后，本文详细分析了采用传统运放共享技术所存在的记忆效应、级间串扰通路 以及和运放共享开关引入的电荷注入和时钟馈通等问题，指出其降低了系统的精 度的原因。 其次，为了消除这些因素对系统精度的影响，提出一种新型适用于运放共享 的双输入开关内置余量增益放大电路(MDAC)，有效地提高了电路的性能。同时 通过对开关内置的双输入 MDAC 电路的分析，提出采用双相交叠时钟来控制运 放共享开关，解决了采用传统非交叠时钟导致的大信号建立恶化等问题。优化了 宽摆幅运放偏置电路，使其与运放获得更好的匹配。 此外，本论文还分析了流水线模数转换器中各种非理想因素对系统的影响， 从真实电路中信号传递和量化的角度，建立了流水线模数转换器的 Matlab 模型， 并引入了诸如电容失配、噪声、运放单位增益带宽、运放压摆率、时钟抖动以及 比较器失调等绝大多数的非理想因素，从而指导电路设计，模型仿真与流片测试 结果相当契合。 本论文在 SMIC 0.18-µm、1.8V 电源电压、单层多晶硅六层金属的标准 CMOS 工艺下，设计实现了一款分辨率为 10bit 采速率为 80MSps 的高精度、低 功耗流水线型模数转换器。在电路设计过程中，本论文也把许多相关的研究论文 作为设计时的参考[51-68]。通过将芯片测试结果与国内外研究的对比，本设计中 的流水线模数转换器在近几年发表的文献中处于较高水平。 最后，为了进一步降低系统功耗，采用了使采样保持电路与第一级 MDAC 共享运放的方法，设计了一款 11bit 的流水线模数转换器。由于采样保持电路和 第一级 MDAC 均对运放功耗有着最高的要求，因此这两者共享运放可以很大程

高精度、低功耗流水线型模数转换器的研究与设计 度上进一步降低系统功耗。同时由于双输入开关内置运放具有良好的级间隔离特 性，可以确保采样保持电路精度不受到共享运放的影响。 1.4论文的组织结构 论文总共分为七章。在本章之后的第二章中，介绍了模数转换器的分类以及 评价指标和测试方法。第三章分别从高精度和低功耗的角度进行分析，介绍了实 现高精度和低功耗所采用的技术方法：分析了各种非理想因素对模数转换器性能 的影响，并在设计的一个Matlab行为级模型中得到了体现。在第四章中，首先 分析了传统运放共享电路中存在的记忆效应、级间信号串扰通路以及共享开关的 电荷注入和时钟馈通等问题对电路精度的影响。之后介绍了前人针对这些问题提 出的一些解决方案，并分析了这些方案中存在的不足。为了更好地解决上述问题， 提出了一种双输入开关内置运放共享的MDAC电路，有效地消除了记忆效应、 级间信号串扰通路，同时解决了共享开关电荷注入和时钟馈通等问题对电路精度 的影响，实现了提高电路性能的目的。第五章则根据提出的新型MDAC结构， 完成了一款10bit80MSps流水线型模数转换器的电路设计和版图布局，给出了 仿真方法和结果。在第六章中，首先制定测试方案，设计测试电路板并搭建了测 试平台。之后对论文设计的模数转换器进行测试，给出了测试结果，并将之与国 内外近期发表在JSSC、ISSCC和CICC等国际顶级期刊和会议的一些高水平研 究成果进行了对比。此外，根据双输入开关内置运放的良好级间隔离特性，提出 了一种使采样保持电路与第一级MDAC共享运放的方法，在保证系统精度的条 件下进一步降低系统功耗。最后，在第七章中对论文进行了总结，给出了结论， 并对未来的研究工作进行了分析和展望。 参考文献 [1]J.Arias,V.Boccuzzi,L.Quintanilla,L.Enriquez,D.Bisbal,M.Banu,and J. Barbolla.Low-Power Pipeline ADC for Wireless LANs [J].IEEE J.Solid-State Circuits, vol.39,pp.1338-1340,Aug.2004. [2]K.Nagaraj,H.S.Fetterman,J.Anidjar,S.H.Lewis,and R.G.Renninger.A 250-mW, 8-b,52-Msamples/s parallel-pipelined A/D converterwith reduced number of amplifiers [J].IEEE J.Solid-State Circuits,vol.32,pp.312-320,Mar.1997. [3]Y.Chiu,P.R.Gray,B.Nikolic.A 14-b 12-MSs CMOS pipeline ADC with over 100-dB SFDR [J].IEEE J.Solid-State Circuits,vol.39,pp.2139-2151,Dec.2004. [4]D.Miyazaki,S.Kawahito and M.Furuta.A 10-b 30-MSs low-power pipelined CMOS AD converter using a pseudodifferential architecture [J].IEEE J.Solid-State Circuits, vol.38,pp.369-373,Feb.2003. [5]A.Matsuzawa,M.Kagawa,M.Kanoh,K.Tatehara,T.Yamaoka,and K.Shimizu.A 10 b 30 MHz two-step parallel BiCMOS ADC with internal S/H.in IEEE Int. 4

高精度、低功耗流水线型模数转换器的研究与设计 4 度上进一步降低系统功耗。同时由于双输入开关内置运放具有良好的级间隔离特 性，可以确保采样保持电路精度不受到共享运放的影响。 1.4 论文的组织结构 论文总共分为七章。在本章之后的第二章中，介绍了模数转换器的分类以及 评价指标和测试方法。第三章分别从高精度和低功耗的角度进行分析，介绍了实 现高精度和低功耗所采用的技术方法；分析了各种非理想因素对模数转换器性能 的影响，并在设计的一个 Matlab 行为级模型中得到了体现。在第四章中，首先 分析了传统运放共享电路中存在的记忆效应、级间信号串扰通路以及共享开关的 电荷注入和时钟馈通等问题对电路精度的影响。之后介绍了前人针对这些问题提 出的一些解决方案，并分析了这些方案中存在的不足。为了更好地解决上述问题， 提出了一种双输入开关内置运放共享的 MDAC 电路，有效地消除了记忆效应、 级间信号串扰通路，同时解决了共享开关电荷注入和时钟馈通等问题对电路精度 的影响，实现了提高电路性能的目的。第五章则根据提出的新型 MDAC 结构， 完成了一款 10bit 80MSps 流水线型模数转换器的电路设计和版图布局，给出了 仿真方法和结果。在第六章中，首先制定测试方案，设计测试电路板并搭建了测 试平台。之后对论文设计的模数转换器进行测试，给出了测试结果，并将之与国 内外近期发表在 JSSC、ISSCC 和 CICC 等国际顶级期刊和会议的一些高水平研 究成果进行了对比。此外，根据双输入开关内置运放的良好级间隔离特性，提出 了一种使采样保持电路与第一级 MDAC 共享运放的方法，在保证系统精度的条 件下进一步降低系统功耗。最后，在第七章中对论文进行了总结，给出了结论， 并对未来的研究工作进行了分析和展望。 参考文献 [1] J. Arias, V. Boccuzzi, L. Quintanilla, L. Enríquez, D. Bisbal, M. Banu, and J. Barbolla.Low-Power Pipeline ADC for Wireless LANs [J]. IEEE J. Solid-State Circuits, vol. 39,pp. 1338–1340, Aug. 2004. [2] K. Nagaraj, H. S. Fetterman, J. Anidjar, S. H. Lewis, and R. G. Renninger.A 250-mW, 8-b, 52-Msamples/s parallel-pipelined A/D converterwith reduced number of amplifiers [J]. IEEE J. Solid-State Circuits, vol. 32, pp. 312–320, Mar. 1997. [3] Y. Chiu, P. R. Gray, B. Nikolic.A 14-b 12-MSs CMOS pipeline ADC with over 100-dB SFDR [J]. IEEE J. Solid-State Circuits, vol. 39,pp. 2139–2151, Dec. 2004. [4] D. Miyazaki, S. Kawahito and M. Furuta.A 10-b 30-MSs low-power pipelined CMOS AD converter using a pseudodifferential architecture [J]. IEEE J. Solid-State Circuits, vol. 38, pp. 369–373, Feb. 2003. [5] A. Matsuzawa, M. Kagawa, M. Kanoh, K. Tatehara, T. Yamaoka, and K. Shimizu.A 10 b 30 MHz two-step parallel BiCMOS ADC with internal S/H. in IEEE Int

第一章前言 Solid-State Circuits Conf.Dig.Tech.Papers,Feb.1990,pp.162-163. [6]P.Vorenkamp and J.P.M.Verdaaskonk.A 10-b 50 Ms/s pipelined ADC.IEEE Int. Solid-State Circuits Conf.Dig.Tech.Papers,Feb.1992,pp.32-33. [7]T.Miki,H.Kouno,T.Kumamoto,Y.Kinoshita,T.Igarashi,and K.Okada.A 10-b 50 MS/s 500-mW A/D converter using a differential voltage subconverter.IEEE J. Solid-State Circuits,vol.29,pp.516-528,Apr.1994. [8]M.P.Flynn and D.J.Allstot.CMOS folding ADC's with currentmode interpolation [C]. IEEE Int.Solid-State Circuits Conf.Dig.Tech.Papers,Feb.1995,pp.274-275. [9]B.Nauta and A.G.W.Venes.A 70-MS/s 110-mW 8-b CMOS folding and interpolating A/D converter [J].IEEE J.Solid-State Circuits,vol.30,pp.1302-1308, Dec.1995. [10]A.G.W.Venes and R.J.van de Plassche.An 80 MHz 80 mW 8 b CMOS folding A/D converter with distributed T/H preprocessing [C].IEEE Int.Solid-State Circuits Conf., Dig.Tech.Papers,Feb.1996,pp.318-319. [11]T.-H.Shu,K.Bacrania,and R.Gokhale.A 10-b 40-Msamples/s BiCMOS A/D converter [J].IEEE J.Solid-State Circuits,vol.31,pp.1507-1510,Oct.1996. [12]M.Yotsuyanagi,T.Etoh,and K.Hirata.A 10-b 50-MHz pipelined CMOS A/D converter with S/H [J].IEEE J.Solid-State Circuits,vol.28,pp.292-300,Mar.1993. [13]C.S.G.Conroy,D.W.Cline,and P.R.Gray.An 8-b 85 MS/s parallel pipeline A/D converter in 1um CMOS [J].IEEE J.Solid-State Circuits,vol.28,pp.447-454,Apr. 1993. [14]K.Nakamura,M.Hotta,L.R.Carley,and D.J.Allstot.An 85 mW,10 b,40 Msample/s CMOS parallel-pipelined ADC [J].IEEE J.Solid-State Circuits,vol.30,pp. 173-183,Mar.1995. [15]T.B.Cho and P.R.Gray.A 10-b,20-Msample/s,35 mW pipeline A/D converter [J]. IEEE J.Solid-State Circuits,vol.30,pp.166-172,Mar.1995. [16]T.C.Choi and R.W.Brodersen.Considerations for high-frequency switched- capacitor filters [J].IEEE Trans.Circuits Syst.,vol.CAS-27,pp.545-552,June 1980 [17]T.Cho,P.R.Gray.A IOb,20Msample/s,35mW Pipelined AID Converter [J].IEEE J. Solid-State Circuits,1995,30(3):166-172 [18]P.T.F.Kwok,H.C.Luong.Power optimization for pipeline analog-to-digital converters [J].IEEE Trans.Circuits Syst.Il:Analog and Digital Signal Processing,1999,46(5): 549-553 [19]E.G.Soenen,L.G.Randall.An architecture and an algorithm for fully digital con ection of monolithic pipeline ADCs [J].IEEE Trans.Circuits Syst.Il:Analog and Digital Signal Processing,1995,42(3):143-153 [20]T.N.Andersen,B.Hernes,A.Briskemyr,et al.A cost-efficient high-speed 12-bit pipeline ADC in 0.18-um digital CMOS [J].IEEE J.Solid-state Circuits,2005,40(7): 1506-1513 [21]J.Bjornsen,T.Ytterdal.Behavioral Modeling and Simulation of Mixed-Signal System-on-a-Chip using System [C].IEEE International Symp.Circuits and Systems. Bangkok,Thailand:IEEE Circuits and Systems Society,2003,25-38 [22]Y.Chiu,P.R.Gray,B.Nikolic.A 14-b 12-MS/s CMOS Pipeline ADC With Over 100dB SFDR [J].IEEE J.Solid-state Circuits,2004,39(12):2139-2151 [23]J.Goes,J.Vital,J.Franca.Systematic design for optimization of high-speed self-calibrated pipelined A/D converters [J].IEEE Trans.Circuits Syst.Il:Analog and 5

第一章 前言 5 Solid-State Circuits Conf. Dig. Tech. Papers, Feb. 1990, pp. 162–163. [6] P. Vorenkamp and J. P. M. Verdaaskonk.A 10-b 50 Ms/s pipelined ADC. IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, Feb. 1992, pp. 32–33. [7] T. Miki, H. Kouno, T. Kumamoto, Y. Kinoshita, T. Igarashi, and K. Okada. A 10-b 50 MS/s 500-mW A/D converter using a differential voltage subconverter. IEEE J. Solid-State Circuits, vol. 29, pp. 516–528, Apr. 1994. [8] M. P. Flynn and D. J. Allstot. CMOS folding ADC’s with currentmode interpolation [C]. IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, Feb. 1995, pp. 274–275. [9] B. Nauta and A. G. W. Venes.A 70-MS/s 110-mW 8-b CMOS folding and interpolating A/D converter [J]. IEEE J. Solid-State Circuits, vol. 30, pp. 1302–1308, Dec. 1995. [10] A. G. W. Venes and R. J. van de Plassche. An 80 MHz 80 mW 8 b CMOS folding A/D converter with distributed T/H preprocessing [C]. IEEE Int. Solid-State Circuits Conf., Dig. Tech. Papers, Feb. 1996, pp.318–319. [11] T.-H. Shu, K. Bacrania, and R. Gokhale.A 10-b 40-Msamples/s BiCMOS A/D converter [J]. IEEE J. Solid-State Circuits, vol. 31, pp. 1507–1510, Oct. 1996. [12] M. Yotsuyanagi, T. Etoh, and K. Hirata.A 10-b 50-MHz pipelined CMOS A/D converter with S/H [J]. IEEE J. Solid-State Circuits, vol. 28, pp. 292–300, Mar. 1993. [13] C. S. G. Conroy, D. W. Cline, and P. R. Gray.An 8-b 85 MS/s parallel pipeline A/D converter in 1μm CMOS [J]. IEEE J. Solid-State Circuits, vol. 28, pp. 447–454, Apr. 1993. [14] K. Nakamura, M. Hotta, L. R. Carley, and D. J. Allstot. An 85 mW, 10 b, 40 Msample/s CMOS parallel-pipelined ADC [J]. IEEE J. Solid-State Circuits, vol. 30, pp. 173–183, Mar. 1995. [15] T. B. Cho and P. R. Gray. A 10-b, 20-Msample/s, 35 mW pipeline A/D converter [J]. IEEE J. Solid-State Circuits, vol. 30, pp. 166–172, Mar. 1995. [16] T. C. Choi and R. W. Brodersen.Considerations for high-frequency switched￾capacitor filters [J]. IEEE Trans. Circuits Syst., vol. CAS-27, pp.545–552, June 1980. [17] T.Cho, P.R. Gray. A IOb, 20Msample/s, 35mW Pipelined AlD Converter [J]. IEEE J. Solid-State Circuits, 1995, 30(3): 166-172 [18] P.T.F. Kwok, H.C. Luong. Power optimization for pipeline analog-to-digital converters [J]. IEEE Trans. Circuits Syst. II: Analog and Digital Signal Processing, 1999, 46 (5): 549-553 [19] E.G. Soenen, L.G. Randall. An architecture and an algorithm for fully digital con ection of monolithic pipeline ADCs [J]. IEEE Trans. Circuits Syst. II: Analog and Digital Signal Processing, 1995, 42 (3):143-153 [20] T.N. Andersen, B. Hernes, A. Briskemyr, et al. A cost-efficient high-speed 12-bit pipeline ADC in 0.18-μm digital CMOS [J]. IEEE J. Solid-state Circuits, 2005, 40(7): 1506-1513 [21] J. Bjornsen, T. Ytterdal. Behavioral Modeling and Simulation of Mixed-Signal System-on-a-Chip using System [C]. IEEE International Symp. Circuits and Systems. Bangkok, Thailand: IEEE Circuits and Systems Society, 2003, 25-38 [22] Y. Chiu, P.R. Gray, B. Nikolic. A 14-b 12-MS/s CMOS Pipeline ADC With Over 100dB SFDR [J]. IEEE J. Solid-state Circuits, 2004, 39(12): 2139-2151 [23] J. Goes, J. Vital, J. Franca. Systematic design for optimization of high-speed self-calibrated pipelined A/D converters [J]. IEEE Trans. Circuits Syst. II: Analog and

高精度、低功耗流水线型模数转换器的研究与设计 Digital Signal Processing,1998,45(12):1513-1526 [24]M.Hershenson.Design of pipeline analog-to-digital converters via geometric programining.IEEE ICCAD.San Jose:the Association for Computing Machinery, 2002,317-324 [25]R.Lotfi,M.T.Sani,M.Y.Azizi,et al.Systematic Design for Power Minimization of Pipelined Analog-to-Digital Converters [C].IEEE ICCAD.San Jose,California,USA: the Association for Computing Machinery,2003,371-374 [26]R.Loth,S.M.Taherzadeh.A 1-V MOSFET-only fully-differential dynamic comparator for use in low-voltage pipelined A/D converters [C].IEEE ISSCS.lasi,Romania: IEEE Circuits and Systems Society,2003,377-380 [27]L.Sumanen,M.Waltari,V.Hakkarainen.CMOS dynamic comparators for pipeline A/D converters [C].IEEE International Symp.Circuits and Systems.Phoenix,Arizona: IEEE Circuits and Systems Society,2002,157-160 [28]P.M.Figueiredo,J.C.Vital.Low kickback noise techniques for CMOS latched comparators [C].IEEE ISCAS.Vancouver,Canada:IEEE Circuits and Systems Society,2004,537-406 [29]U.Koen,S.J.S.Michiel.A 1.8-V 6-Bit 1.3-GHz Flash ADC in 0.25pm CMOS [J].IEEE J.Solid-State Circuits,2003,38(7):1115-1122 [30]P.Uthaichana,E Leelarasmee.Low power CMOS dynamic latch comparators [C]. Conf.Convergent Technologies for Asia-Pacific Region.Bangalore,India:IEEE Circuits andSystems Society,2003,605-608 [31]D.Y.Chang,S.H.Lee.Design techniques for a low-power low-cost CMOS A/D converter [J].IEEE J.Solid-State Circuits,1998,33(8):1244-1248 [32]F.Maloberti,F.Francesconi,P.Malcovati,et al.Design Considerations on Low-Voltage Low-Power Data Converters [J].IEEE Trans.Circuits Syst.I,1995, 42(11):853-863 [33]M.Steyaert,J.Crols,S.Gogaert.Switched opamp,a technique for realizing full CMOS switched-capacitor filters at very low voltages [C].ESSCIRC.Sevilla,Spain: IEEE Solid-State Circuits Society,1993,178-181 [34]M.Bracey,W.R.White,J.Richardson,et al.A full Nyquist 15 MS/s 8-b differential switched-current A/D converter [J].IEEE J.Solid-State Circuits,1996,31(7):945-951 [35]H.O.Hsin,D.L.Bin.A 1-V 9-bit,2.5-Msample/s pipelined ADC with merged switched-opamp and opamp-sharing techniques [C].IEEE International Symp. Circuits and Systems.Kobe,Japan:IEEE Circuits and Systems Society,2005, 1972-1975 [36]M.M.Byung,P.Kim,F.W.Bowman,et al.A 69-mW 10-bit 80-MSample/s Pipelined CMOS ADC [J].IEEE J.Solid-State Circuits,2003,38(12):2031-2039 [37]B.Ginetti and P.G.A.Jespers.A 1.5 Ms/s 8-bit pipeline RSD A/D converter [C]. ESSCIRC Dig.Tech.Papers,Sept.1990,pp.137-140. [38]J.Li and U.K.Moon.A 1.8-V 67-mW 10-bit 100-MSs pipelined ADC using time-shifted CDS technique [J].IEEE J.Solid-State Circuits,vol.39,pp.1476-1468, Sept.2004. [39]S.H.Lewis,H.S.Fetterman,G.F.Gross Jr.,R.Ramachandran,and T.R. Viswanathan.A 10-b 20-Msample/s analog-to-digital converter [J].IEEE J.Solid-State Circuits,vol.27,pp.351-358,Mar.1992. [40]M.Abo and P.R.Gray.A 1.5-V,10-bit,14.3-MS/s CMOS pipeline analog-to-digital 6

高精度、低功耗流水线型模数转换器的研究与设计 6 Digital Signal Processing, 1998, 45(12): 1513-1526 [24] M. Hershenson. Design of pipeline analog-to-digital converters via geometric programining. IEEE ICCAD. San Jose: the Association for Computing Machinery, 2002, 317-324 [25] R. Lotfi, M.T. Sani, M.Y. Azizi, et al. Systematic Design for Power Minimization of Pipelined Analog-to-Digital Converters [C]. IEEE ICCAD. San Jose, California, USA: the Association for Computing Machinery, 2003, 371-374 [26] R. Loth, S.M. Taherzadeh. A 1-V MOSFET-only fully-differential dynamic comparator for use in low-voltage pipelined A/D converters [C]. IEEE ISSCS. Iasi, Romania: IEEE Circuits and Systems Society, 2003, 377-380 [27] L. Sumanen, M. Waltari, V. Hakkarainen. CMOS dynamic comparators for pipeline A/D converters [C]. IEEE International Symp. Circuits and Systems. Phoenix, Arizona: IEEE Circuits and Systems Society, 2002, 157-160 [28] P.M. Figueiredo, J.C. Vital. Low kickback noise techniques for CMOS latched comparators [C]. IEEE ISCAS. Vancouver, Canada: IEEE Circuits and Systems Society, 2004, 537-406 [29] U. Koen, S.J.S. Michiel. A 1.8-V 6-Bit 1.3-GHz Flash ADC in 0.25pm CMOS [J]. IEEE J. Solid-State Circuits, 2003, 38(7): 1115-1122 [30] P. Uthaichana, E Leelarasmee. Low power CMOS dynamic latch comparators [C]. Conf.Convergent Technologies for Asia-Pacific Region. Bangalore, India: IEEE Circuits andSystems Society, 2003, 605-608 [31] D.Y. Chang, S.H. Lee. Design techniques for a low-power low-cost CMOS A/D converter [J].IEEE J. Solid-State Circuits, 1998, 33(8): 1244-1248 [32] F. Maloberti, F. Francesconi, P. Malcovati, et al. Design Considerations on Low-Voltage Low-Power Data Converters [J]. IEEE Trans. Circuits Syst. I, 1995, 42(11): 853-863 [33] M. Steyaert, J. Crols, S. Gogaert. Switched opamp, a technique for realizing full CMOS switched-capacitor filters at very low voltages [C]. ESSCIRC. Sevilla, Spain: IEEE Solid-State Circuits Society, 1993, 178-181 [34] M. Bracey, W.R. White, J. Richardson, et al. A full Nyquist 15 MS/s 8-b differential switched-current A/D converter [J]. IEEE J. Solid-State Circuits, 1996, 31(7): 945-951 [35] H.O. Hsin, D.L. Bin. A 1-V 9-bit, 2.5-Msample/s pipelined ADC with merged switched-opamp and opamp-sharing techniques [C]. IEEE International Symp. Circuits and Systems. Kobe, Japan: IEEE Circuits and Systems Society, 2005, 1972-1975 [36] M.M. Byung, P. Kim, F.W. Bowman, et al. A 69-mW 10-bit 80-MSample/s Pipelined CMOS ADC [J]. IEEE J. Solid-State Circuits, 2003, 38(12): 2031-2039 [37] B. Ginetti and P. G. A. Jespers.A 1.5 Ms/s 8-bit pipeline RSD A/D converter [C]. ESSCIRC Dig. Tech. Papers, Sept. 1990, pp. 137-140. [38] J. Li and U.K. Moon. A 1.8-V 67-mW 10-bit 100-MSs pipelined ADC using time-shifted CDS technique [J]. IEEE J. Solid-State Circuits, vol. 39,pp. 1476-1468, Sept. 2004. [39] S. H. Lewis, H. S. Fetterman, G. F. Gross Jr., R. Ramachandran, and T. R. Viswanathan.A 10-b 20-Msample/s analog-to-digital converter [J].IEEE J. Solid-State Circuits, vol. 27, pp. 351–358, Mar. 1992. [40] M. Abo and P. R. Gray.A 1.5-V, 10-bit, 14.3-MS/s CMOS pipeline analog-to-digital

第一章前言 converter [J].IEEE J.Solid-State Circuits,vol.34,pp.599-606,May 1999. [41]T.Brooks et al.A cascaded sigma-delta pipeline A/D converter with 1.25 MHz signal bandwidth and 89 dB SNR [J].IEEE J.Solid-State Circuits,vol.32,no.12,pp. 1896-1906,Dec.1997. [42]H.Pan,M.Segami,M.Choi,et al.A 3.3-V 12-b 50-MS/s A/D converter in 0.6um CMOS with over 80-dB SFDR [J].IEEE J.Solid-State Circuits,2000,35(12): 1769-1780 [43]M.Choi,A.Asad.A 6-b 1.3-Gsps AD Converter in 0.35).m CMOS [J].IEEE J. Solid-State Circuits,2001,36(12):1847-1858 [44]S.C.Heo,Y.C.Jang,S.H.Park,et al.An 8-bit 200 MSps CMOS folding interpolating ADC with a reduced number of preamplifiers using an averaging technique [C].IEEE ASIC/SOC Conference.Washington DC:IEEE Solid-State Circuits Society,2002, 80-83 [45]Y.M.Lin,B.Kim,P.R.Gray.A 13-b 2.5-MHz self-calibrated pipelined A/D converter in 3-um CMOS.IEEE J.Solid-State Circuits,1991,26(4):628-636 [46]D.A.Mercer.A 12b 750ns Subranging A/D Converter with Self-Correcting S/H.IEEE J.Solid-State Circuits,1991,26(12):1790-1799 [47]Y.B.H.Leung,B.H.Lin.A mismatch-independent DNL pipelined analog-to-digital converter [J].IEEE Trans Circuits Syst.Il:Analog Digital Signal Processing,1999, 46(S:517-526 [48]Li,J.,Zeng,X.,Xie,L.,Chen,J.,Zhang,J.,Guo,Y.A 1.8-V 22-mW 10-bit 30-MS/s Pipelined CMOS ADC for Low-Power Subsampling Applications [J].IEEE J. Solid-State Circuits,2008,43,(2),pp.321-329 [49]S.Ryu,B.Song,K.Bacrania.A 10-bit 50-MS/s Pipelined ADC with Opamp Current Reuse [C].IEEE J.Solid State Circuits,pp.475-485,vol.42,No.3,March 2007 [50]K.Chandrashekar and B.Bakkaloglu.A 10b 50MS/s Opamp-Sharing Pipeline A/D With Current-Reuse OTAs [C].IEEE CICC,Sep.2009,pp.263-266 [51]Mikael Gustavsson,J.Jacob Wiker,Nianxiong Tan.CMOS data converters for communications [M].Kluwer Academic Publishers,2000. [52]Rudy van de Plassche.CMOS integrated analog-to-digital and digital-to-analog converters [M],2nd Edition,Kluwer Academic publishers,2003. [53]Paul R.Gray,Paul J.Hurst,S.H.Lewis,etc.Analysis and design of analog integrated circuits [M],4th Edition,John Wiley Sons,Inc,2000. [54]Behzad Razvi.Principles of data conversion system design [M],The institute of Electrical and Electronics Engineers,Inc,1995. [55]Stephen H.Lewis and Paul R.Gray.A Pipelined 5-Msample/s 9-bit Analog-to-Digital Converter [J].IEEE J.Solid-State Circuits,1987,SC-22(6):954-961. [56]Stephen H Lewis.Optimizing the stage resolution in pipelined,multistage, analog-to-digital converters for video-rate applications [J].IEEE Trans.Circuits and Systems Il:Analog and digital signal processing,1992,39(8):516-523. [57]K.Dyer,D.Fu,S.Lewis,and P.Hurst.Analog background calibration of a 10b 40Msample/s parallel pipelined ADC[C],IEEE Intemnational Solid-State Circuits Conference,February 1998,XLI:142-143. [58]Won-Chul Song,Hae-Wook Choi,Sung-Ung Kwak,and Bang-Sup Song.A 10-b 20-Msample/s low-power CMOS ADC [J].IEEE Journal of Solid-State Circuits,May 1995,30:514-521

第一章 前言 7 converter [J]. IEEE J. Solid-State Circuits, vol. 34, pp.599–606, May 1999. [41] T. Brooks et al.A cascaded sigma-delta pipeline A/D converter with 1.25 MHz signal bandwidth and 89 dB SNR [J]. IEEE J. Solid-State Circuits, vol. 32, no. 12, pp. 1896-1906, Dec. 1997. [42] H.Pan, M.Segami, M.Choi, et al. A 3.3-V 12-b 50-MS/s A/D converter in 0.6um CMOS with over 80-dB SFDR [J]. IEEE J. Solid-State Circuits, 2000, 35(12): 1769-1780 [43] M.Choi, A.Asad. A 6-b 1.3-Gsps AD Converter in 0.35}.m CMOS [J]. IEEE J. Solid-State Circuits, 2001, 36(12): 1847-1858 [44] S.C. Heo, Y.C. Jang, S.H. Park, et al. An 8-bit 200 MSps CMOS folding interpolating ADC with a reduced number of preamplifiers using an averaging technique [C]. IEEE ASIC/SOC Conference. Washington DC: IEEE Solid-State Circuits Society, 2002, 80-83 [45] Y.M. Lin, B. Kim, P.R. Gray. A 13-b 2.5-MHz self-calibrated pipelined A/D converter in 3-μm CMOS. IEEE J. Solid-State Circuits, 1991, 26(4): 628-636 [46] D.A. Mercer. A 12b 750ns Subranging A/D Converter with Self-Correcting S/H. IEEE J.Solid-State Circuits, 1991, 26(12): 1790-1799 [47] Y.B.H. Leung, B.H. Lin. A mismatch-independent DNL pipelined analog-to-digital converter [J]. IEEE Trans Circuits Syst. II: Analog Digital Signal Processing, 1999, 46(S): 517-526 [48] Li, J., Zeng, X., Xie, L., Chen, J., Zhang, J., Guo, Y. A 1.8-V 22-mW 10-bit 30-MS/s Pipelined CMOS ADC for Low-Power Subsampling Applications [J]. IEEE J. Solid-State Circuits, 2008, 43, (2), pp. 321-329 [49] S. Ryu, B. Song, K. Bacrania. A 10-bit 50-MS/s Pipelined ADC with Opamp Current Reuse [C]. IEEE J. Solid State Circuits, pp. 475-485, vol. 42, No. 3, March 2007. [50] K. Chandrashekar and B. Bakkaloglu. A 10b 50MS/s Opamp-Sharing Pipeline A/D With Current-Reuse OTAs [C]. IEEE CICC, Sep. 2009, pp.263-266 [51] Mikael Gustavsson, J. Jacob Wiker, Nianxiong Tan. CMOS data converters for communications [M]. Kluwer Academic Publishers, 2000. [52] Rudy van de Plassche. CMOS integrated analog-to-digital and digital-to-analog converters [M], 2nd Edition, Kluwer Academic publishers, 2003. [53] Paul R. Gray, Paul J. Hurst, S. H. Lewis, etc. Analysis and design of analog integrated circuits [M], 4th Edition, John Wiley & Sons, Inc, 2000. [54] Behzad Razvi. Principles of data conversion system design [M], The institute of Electrical and Electronics Engineers, Inc, 1995. [55] Stephen H. Lewis and Paul R. Gray. A Pipelined 5-Msample/s 9-bit Analog-to-Digital Converter [J]. IEEE J. Solid-State Circuits, 1987, SC-22(6): 954-961. [56] Stephen H Lewis. Optimizing the stage resolution in pipelined, multistage, analog-to-digital converters for video-rate applications [J]. IEEE Trans. Circuits and Systems II: Analog and digital signal processing, 1992, 39(8):516-523. [57] K. Dyer, D. Fu, S. Lewis, and P. Hurst. Analog background calibration of a 10b 40Msample/s parallel pipelined ADC[C], IEEE International Solid-State Circuits Conference, February 1998, XLI: 142 – 143. [58] Won-Chul Song, Hae-Wook Choi, Sung-Ung Kwak, and Bang-Sup Song. A 10-b 20-Msample/s low-power CMOS ADC [J]. IEEE Journal of Solid-State Circuits, May 1995, 30:514 – 521