of them have emitter inputs, however, which must be connected through The families are almost completely pin compatible, but for some mge reason there are a few exceptions. The power pin for dual-in-line sockets is usually #16(or 14)and the ground pin 8(or #7)de- 12.22Mos lOS. where C stands for complementary, which means that both N channel and P chan- ed in a compler ed at 3 to isy. F 54c73 fip-flop has a typical toggle frequency of 4 MHz at 5V and 1F MHz at 10V. If the speed limitations are acceptable, these devices are, on an all-around basis, clearly superior to the other families of logic. They have he lowest power consumption, high noise immmunity(at 10v), symmet rical drive capability at a good cument level and a very high input im- pedance. They are competitive with T L in cost and are approaching T'L in the availability of logic functions, which As contrasted to the other forms of logic, all inputs must be tied to a high or they are open-gate leads of the MOSFETs edev吗s simply do not know where they are if the gate lead is left open. One goo feature is that the inputs can be safety connected to b for a high. Par- ticular attention should be given. to power consumption, which depends strongly on the operating frequency and load The second fom of Mos logic is not really a family of logic elements but a collection of MSi and LSI(large-scale integration)that takes advan tage of the small size and the Low-power consumption of the MOS transis tor to fabricate very large arrays. Typical of these devices are random access memories RAM ad-only memories(ROMs), and microp eres can be made by either n channel or P channel pocesses. They are generally constructed so that their drive levels are
TLcopatible and can be mixed with TL circuits. Many MSI and LSI devices are available in both MOS and T'L. In these cases the T'L is sed only if its superior speed is required 1.2.2.3Ec The last of the logic families to be discussed is coupled logic, or ECL for short. This differs from the oth in that the tramsistors are operated in a linear mode and not allowed to go into saturation. ECL is therefore the fastest of all logic forms. It also con- sumes the most power. ECL devices operate foma-52v power sup ply, a logic low is -1 8V, and a logic high is -0 9V. The output stages are open-ended emitter followers, which are extemally terminated th a 51 resistor to a -2v supply. This clutters up the circuit a bit and the 2v supply because of its low voltage must have a low efficien cy. The basic eCL gate is the OR/NOR as contrasted to the NANd gate for tL 1.2.3 Bullding Blocks There is really not much difference between" basic circuits"and building blocks, except that the term building blocks"implies that the function is contained in one package and is generally more complex The tabulations that follow represent a very coarse selection of some of the more conmmon classifications. A suitable knowledge of the available products muist come from the manufacturers data sheets and not fram a textbook such as thi 1.2.3, 1 Function Generators and Clock Drivers Fumction generator" is a broad term that includes clock generators Clock drivers are included in this section because often the clocks dri many devices and the drive requirements can be quite severe The SN74LS124 is a useful dual voltage-controlled square-wave gen erator.It has a range of 0. 12 Hz to 50 MHz, tunable by a voltage and selectable capacitor. A crystal can also be used in place of the capacitor if desired 23·
The Signetics 555 is very popular basic timer that makes a good square-wave generator up to about 100 khz. It is low in cost, has excel lent stability, and can use 10 Mn resistors to reduce the size of the equired capacit Exar and others make a handy function generator, the XR2206,that gives a choice of sine, triangular, and square-wave outputs over a fre- quency range of 1 Hz to 100 Hz NSC makes wide line of clock drivers. The DS0026 is dual unit that can drive loads up to 1 000 pF at rates as bigh as 5 MHz 1.2.3.2 Flip-Fops In the eady days of digital electronics fip-flops were the basic build ing block. They were used in great quantities to make counters, memo- ries, and mch miscellaneous logic. The design of synchronous counters from flip-flops can be tricky, but now counters of all kinds are available e o kinds of fip-Blopg used the most are the J-K and the D. The J-K nip-nlop has two control line, J and K, which allow four logical operations. The block diagram and the truth table are shown in Fig 1. 10 J-K flip-flops are actuated by a clock edge to do the fumction defined by the J and K inputs, The figure shows a negative edge transi on such as that used on SN7473. Others, for N74109, operate on the positive edge. This device has two principal ap- plications, The first is as part of some overall logic operation. The results of this logic operation are placed on the j and K lines, and the clock then makes Q a high or a low in accordance with the truth tables.This node of operation is used widely in the construction of synchronous counters and various types of memories. The second and more conmmon lication is as a divide-by-2 counter. The f-f is often used following counters to produce a square wave. Fr example, if a counter is used to divide a given frequency by 100, the output has a duty cycle of i to 99 (or sometimes less). Aside from being hard to see on an oscilloscope this may not be a satisfactory waveform. The usual way is to program the
coumter to divide by 50 and then use the f-f to divide by 2, which produe es an exactly symmetrical wave. Most oscillators do not produce a sym ed by designing the oscillator for twice the frequency and following it with an f-f f-f Fl. 1. 10 Truth table of a Kfr Two J-K f-fs can be connected as shown in Fig. 1. 11 to get a syn- hronous divide by 4, and since f-f'a often come two to a package, this is divide by ounter is generally more suitable. The J-K f-f is available with set inputs, which set Q to a low and high respectively. These ing rerride the clock. Then the j and K imputs are combined with various other gates to provide different logical combinations. On these devices th individual truth tables must he shdied to determine their usefulness kL.1lJK÷划4uer Fig 1 12 DaIa aS-R The D f-f is sometimes refered to as a latch or memory element has one input called D, and when the device is clocked, whatever is at D goes to Q. It is also a one-stage shift register, as indicated by Fig.1.12
If there is a high on the input D it is clocked to Q on the rising edge of the clock. However, because of the delay time the input signal does not get to d of the second stage in time to be clocked. The signal must wait for the nex rising edge and consequently is advanced one stag per clock pulse. This is a very useful device and is widely used 1.2.3. 3 Counters and dividers Counters are a very important part of digital circuits and come many varieties. Unfortunately, because of dierent notations, operating techniques, and generally poor application literature they are often confus ing to use and understand. a divider is a special form or use d counter,as is explained in the section that follows. Table 1.3 lists some types THle 1.3 Coumter war 9310 Piogpammahle dacade counter SN4192 Up/down programmble counter Modulo n divider divider ig. 1. 13 illustrates a typical counter. This is a 4-bit device, with the count appearing on the Q lines, A count of 16 is poseible over the range of 0000=0 to 1111= 15. As the clock continues, the count cycles over this range. When the count reaches its maximum value(1111)a pulse appears on the EoC (end of conversion)line. This is the divider output. If all that is required is a division of the clock frequency, the Q inputs are not required. The Eoc pulse is also used in the counting oper- ation.One application is to enable the counters to be used in multistage operations for large counts. a second use is the cormection of the EOC pulse to the P E. (parallel enable) pin to allow programmed counts of less than the maximum. The programming is done by setting the P inputs to the appropriate 1s and 0s. For example, if Po=0, P1=0, P2=1 P3=l. We have the digital number 1100= 12 (remember that Po is LS and P3 is MSB). This would then produce a division of 16-12=4