With each logic element there is a"truth table" that explains how the unit works. These tables are generally in positive logic. This means that the function is described for input signals that are 1s. Negative is when the fumction is described in terme of input zeros. The tive logic is often confusing and is not used in this text. The truth table for the two-input NANd gate is shown in Fig.1. 7. A00 Out B0101 0 Fg.1.7 Troth tble for a NAND gate This table states that if both a and b are“”(∝x团), the ou is a0"(or Lo). It is sometimes easier for the beginner to think in terms d an and gate followed by an inverter. The logic of an ANd gate states that if both A and B are Hi, the output is Hi. An and gate is really a NANd gate followed by an inverter If we look again at the truth table, it also says if A or B areo the output is a I, In other words, the nand circuit does a NaNd fumction with respect to 1s at the input and a NOR function with respect toO's at the input. If the two inputs are tied together, the nANd circuit becomes an inverter. Fig. 1. 8 shows three common symbols. The small circle at the output means inverting, so that if the circles are removed the three symbols become AND, OR, and EXCLUSIVE OR respectively }-[:}=0 (c) HXCI USIVE NOR Fg. 1.8 Some standard gta The ruth tables for the NOR and EXCLUSIVE NOR are shown in Fig. 1.9. The NOR truth tables states that if A or B are a l, the output is a 0. The EXCLUSIVE NOR is the same thing except that the condition
where both A and B are 1s is excluded It is seen that if A or B is a l, one or more of the inputs to the naNd gate are a0. From the truth table of the nand gate we know that this produces a l at its output Inverting the 1 produces a o, and we have a NOR gate. This is a very poor way to make a NOR gate, and not the manner in which they are made. The purpose of the example was to dem onstrate a simple use of the NANd gate and the process by which complex building blocks can be evolved An important diference should be noted at this time between and analog components. There is very little need for the circuit designer to know how a digital fumction is accomplished. If the job is well done, such as propagation delay, power consumption number of leads, and the need for supporting modules will be favorable If the performance specifications of the device are adequate, attempting to udy the technique is generally a waste of time. The reason for this is that a digital device is exact. It or no. This does not mean that it necessarily produces a correct result, but it does produce a defined one The analog word of full of relative numbers and appr which depend heavily on the basic semiconductor properties. These properties are both variant and different from unit to unit. The designer of the digital blocks faces the same problems, but once the digital unit has been properly designed and built, the circuit designer is largely relieved of these considerations 01 0 (a) (b)EX-NOR F. 1.9 Trf tables ea near their maximum speeds they approach a failure mode that analog in nature and all the trou-
bles and uncertainties of the analog circuit are back. 4High-frequency ified in diferent ways. One common expression is "maximum toggle frequency "This means that the output is going be- tween the logic Hi and Lo states at its fastest possible rate but without the duty cycle or rise and fall times defined It does nean that the device can operate properly at that speed. Just how fast the device can operate depends on an analog type of analysis of the system The speed limitations of a digital circuit show up in four different forms: propagation delay, setup time, rise time, and fall time.S)Propa gation delay is basically the time between a signal edges entering a de vice and leaving the device. When a number of digital devices are con nected in series, their propagation delays add up. When a similar set off igital devices are operating in parallel o the tolerance, is not necessarily the This problem is some times referred to as skew. " It is, of course, essential in digital circuits that signal edges occur in a known order. It is a further absolute require- ment that this order preserve a minimum time between signal odges of con- cern. This is called setup time. But simply, a signal must remain at an use of a pull-up resistor in the output cir真 t for a certain minimum amount of time or it will not be recognized The rise and fall times limit the response by not reaching the next gic level in time to be recognized The rise and fall times can be some what controlled through good layout to reduce capacit by limiting the number of stages that are driven, To the toggle frequencies are approached. Much difficulty is avoided if the operating frequencies are limited to one half of the minimum toggle value and if the setup times are increased by a factor of 2 or 3 over the manu- facturers stated minimum values 1.2.2 Family groups A number of different classes of digital circuits are in aurrent use The most popular are T'L, MOS, and ECL a
1221RL TL, which means transistor transistor logic, is most commonly used for small and medium-scale integration(MSI). There are two basic forms ofT'L. The firat and oniginal group has a low-power/low-speed version The later designs are Schottky clamped, which ome in quite a few versions and are still growing. The Schottky diodes are used to prevent the transistors from going into saturation, with a re- sulting increase in apeed for a given power dissipation. This action is de scribed later in this chapter Table 1. 1 and 1.2 give some characteristics of the older families including the 54H74H which is obsolete and used only for replacement The low-power Schottky, S4LS/74LS, and the standard Schottky, 4S/ 74s, have been around for some time. The newer versions include the Fairchild] family 54Fn4F called FAST and two Texas Instruments ver sions, SAS/74AS and 54ALS/4ATS. There are designated Advance hotty and Advanced Low Power Schottky, respectively. All of the TL families represent diiferent tradeoffs between power consumption and The newer families have a higher figure df merit but are somewhat expensive at this time TNe l1 Tld Podt 19 95 DC b MH 54L 33 3 DC b 3 M z 5 19皿W DC b 125 MH 10p 10画W SHT4H 2 mw DCb ME
Tble 1.2 TL characterstic(courtesy T) HpRe如 40A 54L4L -0.1m 20 34 IS74 IS 21 20 -0.36mA 54S7S 28 5 If speed is not required, the Low Power class is a good choice,not only because of low power consumption, but because its low speed makes it insensitive to mamy high-frequency spikes and ditches that are forever appearing where they do not belong in digital circuits The four families of devices can be interconnected if desired, but their input current requirements and output drive capabilities must be ad hered to. The output of each family can sink (low)10 standard loads of its own family and source(high)10 to 20 standard loads of its own family The driving capability is called"fanout Although open inputs to T L logic act as a high, it is not a good actice to leave them disconnected in final circuitry. This is because the also not a safe practice to tie these inputs to the 5V line because the breakdown voltage of the imput lines are only 5. 5v campared to 7V for the supply pin. Unused open inputs can be connected to the output of a spare gate that is held at a high or s I kn resistor can be inserted between the gate lead and the +5v supply. One resistor can be used for up to 25 gates in same logic families. a better way, however, is to use two resis- tors and a couple of microfarads of capacitance to form a stable Hi of about 3. 5V me exception to this is the ls series where most of the devices have diode inputs, which can be directly connected to the + 5v supply. Some 21