Po a PP PE Eoc Eg 1.13 Typical counter An up/down counter used in the down counter mode makes a very convenient programmable counter. It turns out that the programmed input and the coumt are the same. This is not only easy to understand, but also he programming convenient. This is particularly nice with the BCD ver SHn There are, however some complications with this connection, The Fairchild 9316, for example, needs an inverter between the T C.(same as EOC)output and the P. e. input. There is a more subtle reason however, that must be checked in all counters. When the terminal is applied to the parallel enable, the output count is retumed to the value. This, however, is not necesarily a similtaneous process. As soon as one bit is changed, the terminal oount is in the process of disappear- ing. If it disappears before the proper coumt change has been completed ficient delay between the terminal count and the parallel enable 1. 2.3. 4 Shiit Registers Shift registers are, for the most part, easy to understand and use They usually consist of a string of D f-fs. Accordingly, the entire contents of the S-R is moved one position to the right on each clock pulse. There are nomally five classifications: (1)Parallel in/parallel out(bi-directional (2)Paralled in/parallel out ·27
(3)Serial in/parallel ou (4)Parallel in/serial out These are descriptive titles and need little explaining, except haps for one point. All shift registers have a serial output because this is the last bit of a parallel output The bi-directional device is, of course, the moet flexible. It is available in T'L as the SN54194 and in CMOs as the MC14194B. It c move to the left as well as to the right At times the imput logic is different from that of the D f-f. For exam- ple the SN/4195 has a J-K input. This has the truth table shown in Table 1. 4 TaHle 1. 4 Truth tNle ot the SN/4195 hnt SHt聊 d ac first st如alow ShiA and retain first stage I0 Suit and invert finst stage 11貓〓嵫氫卹-,—二 The CMOS. MC14557B is a l-bit to 64-bit variable length S/R, that an be progran ned by six coatrol lines to the desired length 1.2.3.5 Decoders a decoder could be called a line selector This is shown by Fig. 1 14. The two control lineg have four states and therefore any one of four output lines can be seleted. TL generally puts a low on a selected line becanse this form of logic can sink a great deal more curent than it can source. Fairchild has the following products: The 9321 a dual 4 line out/2 line control The 311 a 10 line out/line BCD controt The 9311 a 16 line out/4 line binary control In CMOs the 14555B is a dual 4 line out with a high on the selected line, and the 14556B is the same with' a low on the elected line
1.2, 3.6 The comparator The digital comparator compares ane set of data lines with another set. If the data are the same an output is developed. in the case of the sN7485 there are two additional outputs that state which of the two words is langer. These units can be directly cascaded without extemal A very handy dual 4-bit digital comparator is the Motorola device MC4022 1.2.3.7 The Monostable The monostable and the dia and A/d that are described in the tions that follow are a mixture of digital and analog technologies. There are several all-digital monostables described in the text (consult the in- dex). These are essentially one-shot counters and are necessary in some arrangements. The noumal monostable has an output with a definite time duration. The digital monostable puts out a pulse that is equal to the time required to coumt a given number of clock pulses and starts and finishes in synchronism with the clock. The Fairchild 9602 monostable is a good around device. It can be made to trigger on either rising or falling edges and has complementary outputs. It is retriggerable and has an asynchro- nous reset control. An important feature is that it can also be made nonre- ggerable, as shown in Fig. 1. 15 From the truth table on the data sheets it is Been that the monostable triggers on a L to H if pin 5 is high. However, once the device is fired e changes to a low and any additional pulses do not affect the duration of the pulse. This is therefone a jitter-inhuibiting connection. The 9602 has a
+5￥ 9602 Fg. 1. 15 Nonrctrlgg minimum pulse width of about the circuit shown in Fig. 1. 16 can be used. Here we see that when the input is low, there is a low and a high at the input of the output gate and the output is high. When the input goes high, there are two highs at the input to the output gate and the output drops to a low for the propagation time of the three gates. This is 25 to 55 ns for an SN7400. Ele. 1. 16 Debey m I longer pulse widths are desired, for a given capacitor size, the 96L02( which can use a 200K timing resistor)or the CMOS MC14528 (used at sv for compatibility can be employed These devices are pin compatible. The MC14528, however, has its timing capacitor connected from the resistor to ground. a monostable that can solve some unique prob. ms is the NSC DM7853, which will igger on both t and+edges constables are inherently more sensitive to noise than are standard digital circuits. This is because the noise finds its way to the timing wave- forms which are analog signals. This can cause timing variations and false triggering. In digital circuit where wire wrap is used the timing campo ments are commonly mounted on a cradle adjacent to the monostable. This looks nice, but is bad practice for noise rejection. It is better to solder
the timing components directly to the wire-wrap pins. The noise can also enter the power pin, so that era filtering may be needed at that point. noisy lines should be routed away from the monostable. To summarize monostables are handy devices but should be used only when necessary and then with care 1.2.3.8 D/A and AD Converters he D/A and the A/D, as they are called, are the connecting links between the digital and analog words. They have been around for some time in various forms, but only eecently have the low-cost monolithic units become readily available. These are camplete in and out devices, requir ing only an extemal power supply and the addition of a clock line for the AD. There places on his product, and guidelines for their proper operation must be obtained from the data sheet In the past when only a portion of the total fumction was supplied in package some knowledge of the partial operations was necessary to com plete the overall function. This, now, seems to be pretty mmuch a require ment of the past 调试 decode 解码器 驱动器 v.制作构成 期 短时脉冲 Hi= high ent 优点,价值 微法 单稳态的 31