电子种越女学 University of Electroale Science and Technelery of China 986 Chapter 7 Systolic Architecture Dr.Ling National Key Lab of Science and Technology on Communications
Chapter 7 Systolic Architecture Dr. Ling National Key Lab of Science and Technology on Communications
7.1 Introduction /96 Systolic systems feature modularity and regularity of VLSI design. 丰处 理器 脉动阵列 PE PE PE PE PE This operation is analogous to the flow of blood through the heart,thus named "systolic
7.1 Introduction Systolic systems feature modularity and regularity of VLSI design. This operation is analogous to the flow of blood through the heart, thus named “systolic
7.2 systolic array design methodology /986 Systolic architectures are designed by using linear mapping techniques on regular dependence graphs(DG). Regular Dependence Graph:The presence of an edge in a certain direction at any node in the dG represents presence of an edge in the same direction at all nodes in the DG. ■DG corresponds to space representation→no time instance is assigned to any computation,- t=0. 2021年2月 3
2021年2月 3 7.2 systolic array design methodology Systolic architectures are designed by using linear mapping techniques on regular dependence graphs (DG). Regular Dependence Graph: The presence of an edge in a certain direction at any node in the DG represents presence of an edge in the same direction at all nodes in the DG. DG corresponds to space representation → no time instance is assigned to any computation, → t=0
/96 ■ Systolic architectures have a space-time representation where each node is mapped to a certain processing element(PE)and is scheduled at a particular time instance. ■ Systolic design methodology maps an N- dimensional DG to a lower dimensional systolic architecture. Mapping of N-dimensional DG to (N-1) dimensional systolic array is considered in this chapter. 2021年2月 4
2021年2月 4 Systolic architectures have a space-time representation where each node is mapped to a certain processing element (PE) and is scheduled at a particular time instance. Systolic design methodology maps an Ndimensional DG to a lower dimensional systolic architecture. Mapping of N-dimensional DG to (N-1) dimensional systolic array is considered in this chapter
★ /966 Regular Dependence Graph y(n)=@ox(n)+@x(n-1)+@2x(n-2) x0 xI x2 X3 x4 x5 w2 yo xO 2 w0 wl X0 yl wo y1可y0+w0x0 0 y2 y3 y4 0 1 2 3 4 5 2021年2月 5
2021年2月 5 Regular Dependence Graph 0 1 2 3 4 5 i 2 1 0 x0 x1 x2 x3 x4 x5 y0 y1 y2 y3 y4 y5 w0 w2 w1 w0 w0 y0 x0 y1 x0 y1=y0+w0x0 0 1 2 y n x n x n x n ( ) ( ) ( 1) ( 2)