电子州越女学 University of Electrenie Sciance and Tochnology of China Chapter 3 Pipelining and Parallel Processing Dr.Ling National Key Lab of Science and Technology on Communication
Chapter 3 Pipelining and Parallel Processing Dr. Ling National Key Lab of Science and Technology on Communication
U 3.1 Introduction 966 a(n) b(n) ◆ process time no less than 2Tadder x(n) + y(n) How to increase process time a(n) b(n-1) pipelining D y(n-1) a(2k) b(2k) x(2k) y(2k) Parallel a(2k+1) b(2k+1) x(2k+1) y(2k+1) 2021年2月 2
2021年2月 2 3.1 Introduction process time no less than 2Tadder How to increase process time ? + + a(2k) b(2k) x(2k) y(2k) + + a(2k+1) b(2k+1) x(2k+1) y(2k+1) + + a(n) b(n) x(n) y(n) + + a(n) b(n-1) pipelining D y(n-1) Parallel
986 Pipelining transformation leads to reduction in the critical path,which can be exploited to either increase the clock speed or sample speed or to reduce power consumption at same speed. In parallel processing,multiple outputs are computed in parallel in a clock period. Therefore,the effective sampling speed is increased by the level of parallelism.Similar to the pipelining,parallel processing can also be used for reduction of power consumption. 2021年2月 3
2021年2月 3 Pipelining transformation leads to reduction in the critical path, which can be exploited to either increase the clock speed or sample speed or to reduce power consumption at same speed. In parallel processing, multiple outputs are computed in parallel in a clock period. Therefore, the effective sampling speed is increased by the level of parallelism. Similar to the pipelining, parallel processing can also be used for reduction of power consumption
3.2 Pipelining 966 3 tap FIR filter y(n)=box(n)+bx(n-1)+bx(n-2) x(n) D b0 bl b2 critical path=TM+2TA y(n) The speed of an architecture is limited by the longest path ASIC between any 2 registers or la path 1 海D or between an input and a re path3 Path 4 CLK or between a register/latch al path 2 or between the input and the 2021年2月 4
2021年2月 4 3.2 Pipelining The speed of an architecture is limited by the longest path between any 2 registers or latches or between an input and a register/latch or between a register/latch and an output or between the input and the output. D D X X X + + x(n) y(n) b0 b1 b2 3 tap FIR filter ( ) ( ) ( 1) ( 2) y n b0 x n b1 x n b2 x n critical path=TM+2TA
/966 This longest path or the critical path can be reduced by suitable placing the pipelining registers/latches in the architecture; The pipelining registers/latches can only be placed across any feed-forward cutset of the graph. x(n) D critical path-TM+TA 3 y(n) 1 Clock Input Point 1 Point 2 Point 3 Output 0 X0) ax(0)+bx(-1) 1 X(1) ax(1)+bx(0) ax(0)+bx(-1) 2 X(2) ax(2)+bx(1) ax(1)+bx(0) 3 X3) ax(3)+bx(2) ax(2)+bx(1) cx(0) ax(2)+bx(1)+cx(0)=y2) 2021年2月 5
2021年2月 5 This longest path or the critical path can be reduced by suitable placing the pipelining registers/latches in the architecture; The pipelining registers/latches can only be placed across any feed-forward cutset of the graph. D D X X X + + x(n) y(n) a b c D D critical path=TM+TA Clock Input Point 1 Point 2 Point 3 Output 0 X(0) ax(0)+bx(-1) 1 X(1) ax(1)+bx(0) ax(0)+bx(-1) 2 X(2) ax(2)+bx(1) ax(1)+bx(0) 3 X(3) ax(3)+bx(2) ax(2)+bx(1) cx(0) ax(2)+bx(1)+cx(0)=y(2) 1 2 3