电子科披女学 Uaiversity of Electreaie Selence and Techaolopof Chiaa Chapter 5 Unfolding Dr.Ling National Key Lab of Communication
Chapter 5 Unfolding Dr. Ling National Key Lab of Communication
5.1 Introduction /96 a x(2k) y(n) a 5D, y(2k) x(n) 9D y(2k+1)K 4D x(2k+1) y(n)=ay(n-9)+x(n) a y(2k)=ay(2k-9)+x(2k)=y(2(k-5)+1)+x(2k) y(2k+1)=ay(2k-8)+x(2k+1)=ay(2(k-4)+0)+x(2k+1) 2021年2月 2
2021年2月 2 5.1 Introduction + X x(n) y(n) a 9D + + X X a a 4D 5D x(2k+1) x(2k) y(2k+1) y(2k) y(n) ay(n 9) x(n) y(2k 1) ay(2k 8) x(2k 1) ay(2(k 4) 0) x(2k 1) y(2k) ay(2k 9) x(2k) ay(2(k 5) 1) x(2k)
Unfolding? 96 1. Unfolding is a transformation technique that can be applied to a DSP program to create a new program describing more than one iteration of the original program. 2. Unfolding creates a new programs that describes J consecutive iterations of the original program. 3.Unfolding can be used to reduce sample period and create parallel processing. 2021年2月 3
2021年2月 3 Unfolding? 1. Unfolding is a transformation technique that can be applied to a DSP program to create a new program describing more than one iteration of the original program. 2. Unfolding creates a new programs that describes J consecutive iterations of the original program. 3. Unfolding can be used to reduce sample period and create parallel processing
The applications of unfolding 96 Unfold the program to reveal hidden concurrencies so that the program can be scheduled to a smaller iteration period,thus increasing the throughput of the implementation. Design parallel architectures at the word level and bit level.At the word level,these architectures can be used to design word-parallel architectures from word-serial architectures to increase the throughput or decrease the power consumption.At the bit-level,unfolding can be used to design bit-parallel and digit-serial architectures from bit-serial architectures. 2021年2月 4
2021年2月 4 The applications of unfolding Unfold the program to reveal hidden concurrencies so that the program can be scheduled to a smaller iteration period, thus increasing the throughput of the implementation. Design parallel architectures at the word level and bit level. At the word level, these architectures can be used to design word-parallel architectures from word-serial architectures to increase the throughput or decrease the power consumption. At the bit-level, unfolding can be used to design bit-parallel and digit-serial architectures from bit-serial architectures
5.2 Unfolding algorithm 95 The J unfolded program contains J times as many nodes and edges as the original DFG. For each node U in the original DFG,draw the J nodes Uo,U,...,U-1. s For each edge U->V with w delays in the original FG,draw the edges U withdelays fori=0,1,..,J-1. 2021年2月 5
2021年2月 5 5.2 Unfolding algorithm The J unfolded program contains J times as many nodes and edges as the original DFG. For each node U in the original DFG, draw the J nodes U0 ,U1 ,…,UJ-1 . For each edge UV with w delays in the original DFG, draw the J edges UiV(i+w)%J with delays for i=0,1,…,J-1. J i w J i w