《数字电路》课程教学资源：《digital design principles & practices》参考书籍PDF英文版（John Wakerly，3rd edition）.pdf_P16-P20

16 Chapter 1 Introduction DO NOT COPY DO NOT COPY DO NOT COPY DO NOT COPY DO NOT COPY DO NOT COPY DO NOT COPY DO NOT COPY DO NOT COPY Copyright © 1999 by John F. Wakerly Copying Prohibited Proponents of one approach or the other used to get into “religious” arguments over which way was better, but the largest manufacturer of large programmable logic devices, Xilinx Corporation, acknowledges that there is a place for both approaches and manufactures both types of devices. What’s more important than chip architecture is that both approaches support a style of design in which products can be moved from design concept to prototype and production in a very period of time short time. Also important in achieving short “time-to-market” for all kinds of PLDbased products is the use of HDLs in their design. Languages like ABEL and VHDL, and their accompanying software tools, allow a design to be compiled, synthesized, and downloaded into a PLD, CPLD, or FPGA literally in minutes. The power of highly structured, hierarchical languages like VHDL is especially important in helping designers utilize the hundreds of thousands or millions of gates that are provided in the largest CPLDs and FPGAs. 1.8 Application-Specific ICs Perhaps the most interesting developments in IC technology for the average digital designer are not the ever-increasing chip sizes, but the ever-increasing opportunities to “design your own chip.” Chips designed for a particular, limited product or application are called semicustom ICs or application-specific ICs (ASICs). ASICs generally reduce the total component and manufacturing cost of a product by reducing chip count, physical size, and power consumption, and they often provide higher performance. The nonrecurring engineering (NRE) cost for designing an ASIC can exceed the cost of a discrete design by $5,000 to $250,000 or more. NRE charges are paid to the IC manufacturer and others who are responsible for designing the PLD PLD PLD PLD PLD PLD PLD PLD Programmable Interconnect (a) (b) = logic block Figure 1-6 Large programmable-logic-device scaling approaches: (a) CPLD; (b) FPGA. semicustom IC application-specific IC (ASIC) nonrecurring engineering (NRE) cost

Section 1.8 Application-Specific ICs 17 internal structure of the chip,creating tooling such as the metal masks for manu- facturing the chips,developing tests for the manufactured chips,and actually making the first few sample chips. The NRE cost for a typical,medium-complexity ASIC with about 100,000 gates is $30-$50,000.An ASIC design normally makes sense only when the NRE cost can be offset by the per-unit savings over the expected sales volume of the product The NRE cost to design a custom LS/chip-a chip whose functions,inter- custom LSI nal architecture,and detailed transistor-level design is tailored for a specific custome is very high,$250,000 or more.Thus,full custom LSI design is done only for chips that have general commercial application or that will enjoy very high sales volume in a specific application(e.g.,a digital watch chip,a network interface,or a bus-interface circuit for a PC). To reduce NRE charges,IC manufacturers have developed libraries of standard cells including commonly used MSI functions such as decoders, standard cells registers,and counters,and commonly used LSI functions such as memories, programmable,and Inastandard-celldesigm the standard-cell design logic designer interconnects functions in much the same way as in a multichip MSI/LSI design.Custom cells are created (at added cost,of course)only if abso- lutely necessary.All of the cells are then laid out on the chip,optimizing the layout to reduce propagation delays and minimize the size of the chip.Minimiz ing the chip size reduces the per-unit cost of the chip.since it increases the number of chips that can be fabricated on a single wafer.The NRE cost for a standard-celld ally on the order of$150,000. Well,$150,000 is still a lot of money for most folks,so IC manufacturers have gone one step further to bring ASIC design capability to the masses.A gate ray is an IC whose internal structure is an array of gates whose interconnec gate array tions are initially unspecified.The logic designer specifies the gate types and interconnections.Even though the chip design is ultimately specified at this very low level,the designer typically works with"macrocells."the same high-level functions used in multichip MSI/LSI and standard-cell designs;software expands the high-level design into a low-level one. The main difference between standard-cell and gate-array design is that the macrocells and the chip layout of a gate array are not as highly optimized as hose in a standard-cell design,so the chip may be 25%or more larger,and therefore may cost more.Also,there is no opportunity to create custom cells in the gate-array approach.On the other hand,a gate-array design can be complet- ed faster and at lower NRE cost,ranging from about $5000(what you're told initially)to $75,000(what you find you've spent when you're all done). The basic digital design methods that you'll study throughout this book apply very well to the functional design of ASICs.However,there are additional opportunities,constraints,and steps in ASIC design,which usually depend on the particular ASIC vendor and design environment. Copyright 1999 by John F.Wakerly Copying Prohibited

Section 1.8 Application-Specific ICs 17 DO NOT COPY DO NOT COPY DO NOT COPY DO NOT COPY DO NOT COPY DO NOT COPY DO NOT COPY DO NOT COPY DO NOT COPY Copyright © 1999 by John F. Wakerly Copying Prohibited internal structure of the chip, creating tooling such as the metal masks for manufacturing the chips, developing tests for the manufactured chips, and actually making the first few sample chips. The NRE cost for a typical, medium-complexity ASIC with about 100,000 gates is $30–$50,000. An ASIC design normally makes sense only when the NRE cost can be offset by the per-unit savings over the expected sales volume of the product. The NRE cost to design a custom LSI chip—a chip whose functions, internal architecture, and detailed transistor-level design is tailored for a specific customer—is very high, $250,000 or more. Thus, full custom LSI design is done only for chips that have general commercial application or that will enjoy very high sales volume in a specific application (e.g., a digital watch chip, a network interface, or a bus-interface circuit for a PC). To reduce NRE charges, IC manufacturers have developed libraries of standard cells including commonly used MSI functions such as decoders, registers, and counters, and commonly used LSI functions such as memories, programmable logic arrays, and microprocessors. In a standard-cell design, the logic designer interconnects functions in much the same way as in a multichip MSI/LSI design. Custom cells are created (at added cost, of course) only if absolutely necessary. All of the cells are then laid out on the chip, optimizing the layout to reduce propagation delays and minimize the size of the chip. Minimizing the chip size reduces the per-unit cost of the chip, since it increases the number of chips that can be fabricated on a single wafer. The NRE cost for a standard-cell design is typically on the order of $150,000. Well, $150,000 is still a lot of money for most folks, so IC manufacturers have gone one step further to bring ASIC design capability to the masses. A gate array is an IC whose internal structure is an array of gates whose interconnections are initially unspecified. The logic designer specifies the gate types and interconnections. Even though the chip design is ultimately specified at this very low level, the designer typically works with “macrocells,” the same high-level functions used in multichip MSI/LSI and standard-cell designs; software expands the high-level design into a low-level one. The main difference between standard-cell and gate-array design is that the macrocells and the chip layout of a gate array are not as highly optimized as those in a standard-cell design, so the chip may be 25% or more larger, and therefore may cost more. Also, there is no opportunity to create custom cells in the gate-array approach. On the other hand, a gate-array design can be completed faster and at lower NRE cost, ranging from about $5000 (what you’re told initially) to $75,000 (what you find you’ve spent when you’re all done). The basic digital design methods that you’ll study throughout this book apply very well to the functional design of ASICs. However, there are additional opportunities, constraints, and steps in ASIC design, which usually depend on the particular ASIC vendor and design environment. custom LSI standard cells standard-cell design gate array

18 Chapter 1 Introduction 1.9 Printed-Circuit Boards printed-circuit board An IC is normally mounted on a printed-circuit board (PCB)[or printed-wiring (PCB) board(PWB)]that connects it to other ICs in a system.The multilayer PCBs of fiberglass that are laminated into a single board about 1/16 inch thick. PCB traces Individual wire connections,or PCB traces are usually quite narrow,10 to mil 25 mils in typical PCBs.(A milisone-thousandth of an inch.)PCB fine-line technology,the traces are extremely narrow,as little as 4 mils wide with 4-mil spacing between adjacent traces.Thus,up to 125 connections may be routed in a one-inch-wide band on a single layer of the PCB.If higher connection density is needed,then more layers are used. surface-mount Most of the components in modern PCBs use surface-mount technology technology (SMT) (SMT).Instead of having the long pins of DIP packages that poke through the board and are soldered to the underside,the leads of SMT IC packages are bent to make flat contact with the top surface of the PCB.Before such components are mounted on the PCB,a special"solder paste"is applied to contact pads on the PCB using a stencil whose hole pattern matches the contact pads to be soldered.Then the SMT components are placed(by hand or by machine)on the pads,where they are held in place by the solder paste (or in some cases,by glue). Finally,the entire assembly is passed through an oven to melt the solder paste. which then solidifies when cooled Surface-mount component technology,coupled with fine-line PCB tech- nology,allows extremely dense packing of integrated circuits and other mponents on a PCB.This dense packing does more than save space.For very high-speed circuits,dense packing goes a long way toward minimizing adverse analog phenomena,including transmission-line effects and speed-of-light limitations. To satisfy the most stringent requirements for speed and density, modules (MCMs)have been developed.In this technology,IC dice are not mounted in individual plastic or ceramic packages.Instead,the IC dice for a high-speed subsystem (say,a proc cessor and its cache memory)are bonded directly to a substrate that contains the required interconnections on multiple layers.The MCM is hermetically sealed and has its own external pins for power, ground,and just those signals that are required by the system that contains it. 1.10 Digital-Design Levels Digital design can be carried out at several different levels of representation and abstraction.Although you may learn and practice design at a particular level. from time to time you'll need to go up or down a level or two to get the job done. Also,the industry itself and most designers have been steadily moving to highe levels of abstraction as circuit density and functionality have increased Copyright 1999 by John F.Wakerly Copying Prohibited

18 Chapter 1 Introduction DO NOT COPY DO NOT COPY DO NOT COPY DO NOT COPY DO NOT COPY DO NOT COPY DO NOT COPY DO NOT COPY DO NOT COPY Copyright © 1999 by John F. Wakerly Copying Prohibited 1.9 Printed-Circuit Boards An IC is normally mounted on a printed-circuit board (PCB) [or printed-wiring board (PWB)] that connects it to other ICs in a system. The multilayer PCBs used in typical digital systems have copper wiring etched on multiple, thin layers of fiberglass that are laminated into a single board about 1/16 inch thick. Individual wire connections, or PCB traces are usually quite narrow, 10 to 25 mils in typical PCBs. (A mil is one-thousandth of an inch.) In fine-line PCB technology, the traces are extremely narrow, as little as 4 mils wide with 4-mil spacing between adjacent traces. Thus, up to 125 connections may be routed in a one-inch-wide band on a single layer of the PCB. If higher connection density is needed, then more layers are used. Most of the components in modern PCBs use surface-mount technology (SMT). Instead of having the long pins of DIP packages that poke through the board and are soldered to the underside, the leads of SMT IC packages are bent to make flat contact with the top surface of the PCB. Before such components are mounted on the PCB, a special “solder paste” is applied to contact pads on the PCB using a stencil whose hole pattern matches the contact pads to be soldered. Then the SMT components are placed (by hand or by machine) on the pads, where they are held in place by the solder paste (or in some cases, by glue). Finally, the entire assembly is passed through an oven to melt the solder paste, which then solidifies when cooled. Surface-mount component technology, coupled with fine-line PCB technology, allows extremely dense packing of integrated circuits and other components on a PCB. This dense packing does more than save space. For very high-speed circuits, dense packing goes a long way toward minimizing adverse analog phenomena, including transmission-line effects and speed-of-light limitations. To satisfy the most stringent requirements for speed and density, multichip modules (MCMs) have been developed. In this technology, IC dice are not mounted in individual plastic or ceramic packages. Instead, the IC dice for a high-speed subsystem (say, a processor and its cache memory) are bonded directly to a substrate that contains the required interconnections on multiple layers. The MCM is hermetically sealed and has its own external pins for power, ground, and just those signals that are required by the system that contains it. 1.10 Digital-Design Levels Digital design can be carried out at several different levels of representation and abstraction. Although you may learn and practice design at a particular level, from time to time you’ll need to go up or down a level or two to get the job done. Also, the industry itself and most designers have been steadily moving to higher levels of abstraction as circuit density and functionality have increased. printed-circuit board (PCB) printed-wiring board (PWB) PCB traces mil fine-line surface-mount technology (SMT) multichip module (MCM)

Section1.10 Digital-Design Levels 9 The lowest level of digital design is device physics and IC manufacturing processes.This is the level that is primarily responsible for the breathtaking advances in IC speed and density that have occurred over the past decades.The effects of these advances are summarized in Moore's Law,first stated by Intel Moore's Law founder Gordon Moore in 1965:that the number of transistors per square inch in an IC doubles every year.In recent years,the rate ofadvance has slowed down to doubling about every 18 months,bu it is important to note that with each ou bling of density has also come a doubling of speed. This book does not reach down to the level of device physics and IC but the importance of thatevel.Being aware of likely technology advances and other changes is important in system and product planning.For example,decreases in chip geometries have recently lar systems and upgrades In this book,we jump into digital design at the transistor level and go all the way up to the level of logic design using HDLs.We stop short of the next evel,which includes computer design and overall system design.The “center of our discussion is at the level of functional building blocks. To get a preview of the levels of design that we'll cover,consider a simple A design example.Suppose you are to build a"multiplexer"with two data input bits,A and B.a control input bitS,and an output bit Z.Depending on the value ofS,0 or 1,the circuit is to transfer the value of either A or B to the output Z.This c idea is illustrated in the"switch model"of Figure 1-7.Let us consider the design of this functio n at seve eral different levels Figure 1-7 Although logic design is usually carried out at higher level,for some func- lel for tions it is advantageous to optimize them by designing at the transistor level.The multiplexer is such a function.Figure 1-8 shows how the multiplexer can be designed in"CMOS"technology using specialized transistor circuit structures Figure 1-8 Multiplexer design using CMOS transmission gates. COPY Copyright 1999 by John F.Wakerly Copying Prohibited

Section 1.10 Digital-Design Levels 19 DO NOT COPY DO NOT COPY DO NOT COPY DO NOT COPY DO NOT COPY DO NOT COPY DO NOT COPY DO NOT COPY DO NOT COPY Copyright © 1999 by John F. Wakerly Copying Prohibited The lowest level of digital design is device physics and IC manufacturing processes. This is the level that is primarily responsible for the breathtaking advances in IC speed and density that have occurred over the past decades. The effects of these advances are summarized in Moore’s Law, first stated by Intel founder Gordon Moore in 1965: that the number of transistors per square inch in an IC doubles every year. In recent years, the rate of advance has slowed down to doubling about every 18 months, but it is important to note that with each doubling of density has also come a doubling of speed. This book does not reach down to the level of device physics and IC processes, but you need to recognize the importance of that level. Being aware of likely technology advances and other changes is important in system and product planning. For example, decreases in chip geometries have recently forced a move to lower logic-power-supply voltages, causing major changes in the way designers plan and specify modular systems and upgrades. In this book, we jump into digital design at the transistor level and go all the way up to the level of logic design using HDLs. We stop short of the next level, which includes computer design and overall system design. The “center” of our discussion is at the level of functional building blocks. To get a preview of the levels of design that we’ll cover, consider a simple design example. Suppose you are to build a “multiplexer” with two data input bits, A and B, a control input bit S, and an output bit Z. Depending on the value of S, 0 or 1, the circuit is to transfer the value of either A or B to the output Z. This idea is illustrated in the “switch model” of Figure 1-7. Let us consider the design of this function at several different levels. Although logic design is usually carried out at higher level, for some functions it is advantageous to optimize them by designing at the transistor level. The multiplexer is such a function. Figure 1-8 shows how the multiplexer can be designed in “CMOS” technology using specialized transistor circuit structures Moore’s Law A B Z S Figure 1-7 Switch model for multiplexer function. A B S VCC Z Figure 1-8 Multiplexer design using CMOS transmission gates

20 Chapter 1 Introduction DO NOT COPY DO NOT COPY DO NOT COPY DO NOT COPY DO NOT COPY DO NOT COPY DO NOT COPY DO NOT COPY DO NOT COPY Copyright © 1999 by John F. Wakerly Copying Prohibited called “transmission gates,” discussed in Section 3.7.1. Using this approach, the multiplexer can be built with just six transistors. Any of the other approaches that we describe require at least 14 transistors. In the traditional study of logic design, we would use a “truth table” to describe the multiplexer’s logic function. A truth table list all possible combinations of input values and the corresponding output values for the function. Since the multiplexer has three inputs, it has 23 or 8 possible input combinations, as shown in the truth table in Table 1-1. Once we have a truth table, traditional logic design methods, described in Section 4.3, use Boolean algebra and well understood minimization algorithms to derive an “optimal” two-level AND-OR equation from the truth table. For the multiplexer truth table, we would derive the following equation: This equation is read “Z equals not S and A or S and B.” Going one step further, we can convert the equation into a corresponding set of logic gates that perform the specified logic function, as shown in Figure 1-9. This circuit requires 14 transistors if we use standard CMOS technology for the four gates shown. A multiplexer is a very commonly used function, and most digital logic technologies provide predefined multiplexer building blocks. For example, the 74x157 is an MSI chip that performs multiplexing on two 4-bit inputs simultaneously. Figure 1-10 is a logic diagram that shows how we can hook up just one bit of this 4-bit building block to solve the problem at hand. The numbers in color are pin numbers of a 16-pin DIP package containing the device. Table 1-1 Truth table for the multiplexer function. SAB Z 000 0 001 0 010 1 011 1 100 0 101 1 110 0 111 1 Z = S′ ⋅ A + S ⋅ B A S B Z SN ASN SB Figure 1-9 Gate-level logic diagram for multiplexer function