Section 1.10 Digital-Design Levels 21 74x157 A 2Y 11 3A 10 3Y Figure 1-10 Logic diagram for a 13 4B 4Y We can also realize the multiplexer function as part of a programmable logic device.Languages like ABEL allow us to specify outputs using Boolean equations similar to the one on the previous page,but it's usually more conve- nient to use "higher-level"language elements.For example,Table 1-2 is an name of th will be realized.The next two lines specify the device pin numbers for inputs and output.The"WHEN"statement specifies the actual logic function in a way that's very easy to understand,even though we haven't covered ABEL yet An even higher level language,VHDL,can be used to specify the multi- plexer function in a way that is very flexible and hierarchical.Table 1-3 is an example VHDL program for the multiplexer.The first two lines specify a standard library and set of definitions to use in the design.The next four lines specify only the inputs and outputs of the function,and purposely hide any details about the way the function is realized internally.The "architecture" section of the program specifies the function's behavior.VHDL syntax takesa little getting used to,but the single "when"statement says basically the same thing that the ABEL version did.A VHDL "synthesis tool"can start with this module chapimux Table 1-2 ABEL program for the multiplexer 28,8 g盟6a3e‘eoe equations WHEN S ==0 THEN Z A;ELSE Z B: end chapimux Copyright 1999 by John F.Wakerly Copying Prohibited
Section 1.10 Digital-Design Levels 21 DO NOT COPY DO NOT COPY DO NOT COPY DO NOT COPY DO NOT COPY DO NOT COPY DO NOT COPY DO NOT COPY DO NOT COPY Copyright © 1999 by John F. Wakerly Copying Prohibited We can also realize the multiplexer function as part of a programmable logic device. Languages like ABEL allow us to specify outputs using Boolean equations similar to the one on the previous page, but it’s usually more convenient to use “higher-level” language elements. For example, Table 1-2 is an ABEL program for the multiplexer function. The first three lines define the name of the program module and specify the type of PLD in which the function will be realized. The next two lines specify the device pin numbers for inputs and output. The “WHEN” statement specifies the actual logic function in a way that’s very easy to understand, even though we haven’t covered ABEL yet. An even higher level language, VHDL, can be used to specify the multiplexer function in a way that is very flexible and hierarchical. Table 1-3 is an example VHDL program for the multiplexer. The first two lines specify a standard library and set of definitions to use in the design. The next four lines specify only the inputs and outputs of the function, and purposely hide any details about the way the function is realized internally. The “architecture” section of the program specifies the function’s behavior. VHDL syntax takes a little getting used to, but the single “when” statement says basically the same thing that the ABEL version did. A VHDL “synthesis tool” can start with this module chap1mux title 'Two-input multiplexer example' CHAP1MUX device 'P16V8' A, B, S pin 1, 2, 3; Z pin 13 istype 'com'; equations WHEN S == 0 THEN Z = A; ELSE Z = B; end chap1mux Table 1-2 ABEL program for the multiplexer. 74x157 1A 1B 2A 2B 3A 3B 4A 4B G 2 4 1Y 7 2Y 9 3Y 12 4Y 3 5 6 11 10 14 13 S 1 15 S B A Z Figure 1-10 Logic diagram for a multiplexer using an MSI building block
22 Chapter 1 Introduction Table 1-3 VHDL program for the multiplexer entity Vchapimux is port A,B,S:in STD_LOGIC: 7: out STD_LOGIC ) end Vchapimux; architecture Vchapimux_arch of Vchapimux is begin A when S0 else B; end Vchapimux_arch; behavioral description and produce a circuit that has this behavior in a specified target digital-logi c technology By explicitly enforcing a separation of input/output definitions("entity") and internal realization("architecture"),VHDL makes it easy for designers to define alternate realizations of functions without having to make changes else- where in the design hierarchy. For example,a designer could specify an alternate,structural architecture for the multiplexer as shown in Table 1-4.This architecture is basically a text equivalent of the logic diagram in Figure 1-9. Going one step further,VHDL is powerful enough that we could actually define operations that model functional behavioral at the transistor level (though we won't explore such capabilities in this book).Thus,we could come full circle Table 1-4 architecture Vchapimux rch of Vchapimux is "Structural"VHDL signal SN,ASN,SB:STD LOGIC: program for the begin multiplexer. U1:INV (S,SN); _gate_arch 1.11 The Name of the Game Given the functional and performance requirements for a digital system,the board-level design name of the game in practical digital design is to minimize cost.For board-level designs-systems that are packaged on a single PCB-this usually means min- ber of IC packages.If too many ICs are required,they we on't all fit on the PCB."Well,just use a bigger PCB,"you say.Unfortunately,PCB sizes are usually constrained by factors such as pre-existing standards (e.g.,add-in Copyright1999 by John F.Wakerly Copying Prohibited
22 Chapter 1 Introduction DO NOT COPY DO NOT COPY DO NOT COPY DO NOT COPY DO NOT COPY DO NOT COPY DO NOT COPY DO NOT COPY DO NOT COPY Copyright © 1999 by John F. Wakerly Copying Prohibited behavioral description and produce a circuit that has this behavior in a specified target digital-logic technology. By explicitly enforcing a separation of input/output definitions (“entity”) and internal realization (“architecture”), VHDL makes it easy for designers to define alternate realizations of functions without having to make changes elsewhere in the design hierarchy. For example, a designer could specify an alternate, structural architecture for the multiplexer as shown in Table 1-4. This architecture is basically a text equivalent of the logic diagram in Figure 1-9. Going one step further, VHDL is powerful enough that we could actually define operations that model functional behavioral at the transistor level (though we won’t explore such capabilities in this book). Thus, we could come full circle by writing a VHDL program that specifies a transistor-level realization of the multiplexer equivalent to Figure 1-8. 1.11 The Name of the Game Given the functional and performance requirements for a digital system, the name of the game in practical digital design is to minimize cost. For board-level designs—systems that are packaged on a single PCB—this usually means minimizing the number of IC packages. If too many ICs are required, they won’t all fit on the PCB. “Well, just use a bigger PCB,” you say. Unfortunately, PCB sizes are usually constrained by factors such as pre-existing standards (e.g., add-in Table 1-3 VHDL program for the multiplexer. library IEEE; use IEEE.std_logic_1164.all; entity Vchap1mux is port ( A, B, S: in STD_LOGIC; Z: out STD_LOGIC ); end Vchap1mux; architecture Vchap1mux_arch of Vchap1mux is begin Z <= A when S = '0' else B; end Vchap1mux_arch; Table 1-4 “Structural” VHDL program for the multiplexer. architecture Vchap1mux_gate_arch of Vchap1mux is signal SN, ASN, SB: STD_LOGIC; begin U1: INV (S, SN); U2: AND2 (A, SN, ASN); U3: AND2 (S, B, SB); U4: OR2 (ASN, SB, Z); end Vchap1mux_gate_arch; board-level design
Section 1.12 Going Forward 23 boards for PCs),packaging constraints(e.g.,it has to fit in a toaster),or edicts from above(e.g.,in order to get the project approved three months ago,you fool- ishly told your manager that it would all fit on a 3x5 inch PCB,and now you've got to deliver!).In each of these cases,the cost of using a larger PCB or multiple PCBs may be unacceptable. Minimizing the number of ICs is usually the rule even though individual IC costs vary.For example,a typical SSIor MSI IC may cost 25 cents,while an small PLD may cost a dollar.It may be possible to perform a particular function with three SSI and MSI ICs(75 cents)or one PLD(a dollar).In most situations. the m ore expensive PLD solution is used,not because the designer owns stock in the IC company,but because the PLD solution uses less PCB area and is also a lot easier to change if it's not right the first time. In ASIC design,the name of the game is a little different,but the impor- ASIC design tance of structured,functional design techniques is the same.Although it's easy to burn hours and weeks creating custom macrocells and minimizing the total gate count of an ASIC,only rarely is this advisable.The per-unit cost reduction achieved by having a%smaller chip is negligible except in high-volume applications.In applications with low to medium volume(the majority),two other factors are more important:design time and NRE cost. A shorter design time allows a product to reach the market sooner,increas- ing revenues over the lifetime of the product.A lower NRE cost also flows right to the"bottom line,"and in small companies may be the only way the project can be completed before the company runs out of money (believe me,I've been there!).If the product is suc cessful,it's always possible and desi late to reduce perunit costs Thened o time and NRE cost argues in favor of a structured,as opposed to highly opti- mized,approach toASICdesign,using standard building blocks provided in the ASIC manufacturer's library. The considerations in PLD,CPLD,and FPGA design are a combination of the above.The choice of a particular PLD technology and device size is usually made fairly early in the design cycle.Later,as long as the design"fits"in the selected device,there's no point in trying to optimize gate count or board area- the device has already been committed.However,if new functions or bug fixes push the design beyond the capacity of the selected device that's when you mus work very hard to modify the design to make it fit. 1.12 Going Forward This concludes the introductory chapter.As you continue reading this book keep in mind two things.First,the ultimate goal of digital design is to build systems that solve problems for people.While this book will give you the basic tools for design,it's still your job to keep"the big picture"in the back of your mind.Second,cost is an important factor in every design decision;and you must Copyright 1999 by John F.Wakerly Copying Prohibited
Section 1.12 Going Forward 23 DO NOT COPY DO NOT COPY DO NOT COPY DO NOT COPY DO NOT COPY DO NOT COPY DO NOT COPY DO NOT COPY DO NOT COPY Copyright © 1999 by John F. Wakerly Copying Prohibited boards for PCs), packaging constraints (e.g., it has to fit in a toaster), or edicts from above (e.g., in order to get the project approved three months ago, you foolishly told your manager that it would all fit on a 3 × 5 inch PCB, and now you’ve got to deliver!). In each of these cases, the cost of using a larger PCB or multiple PCBs may be unacceptable. Minimizing the number of ICs is usually the rule even though individual IC costs vary. For example, a typical SSI or MSI IC may cost 25 cents, while an small PLD may cost a dollar. It may be possible to perform a particular function with three SSI and MSI ICs (75 cents) or one PLD (a dollar). In most situations, the more expensive PLD solution is used, not because the designer owns stock in the IC company, but because the PLD solution uses less PCB area and is also a lot easier to change if it’s not right the first time. In ASIC design, the name of the game is a little different, but the importance of structured, functional design techniques is the same. Although it’s easy to burn hours and weeks creating custom macrocells and minimizing the total gate count of an ASIC, only rarely is this advisable. The per-unit cost reduction achieved by having a 10% smaller chip is negligible except in high-volume applications. In applications with low to medium volume (the majority), two other factors are more important: design time and NRE cost. A shorter design time allows a product to reach the market sooner, increasing revenues over the lifetime of the product. A lower NRE cost also flows right to the “bottom line,” and in small companies may be the only way the project can be completed before the company runs out of money (believe me, I’ve been there!). If the product is successful, it’s always possible and profitable to “tweak” the design later to reduce per-unit costs. The need to minimize design time and NRE cost argues in favor of a structured, as opposed to highly optimized, approach to ASIC design, using standard building blocks provided in the ASIC manufacturer’s library. The considerations in PLD, CPLD, and FPGA design are a combination of the above. The choice of a particular PLD technology and device size is usually made fairly early in the design cycle. Later, as long as the design “fits” in the selected device, there’s no point in trying to optimize gate count or board area— the device has already been committed. However, if new functions or bug fixes push the design beyond the capacity of the selected device, that’s when you must work very hard to modify the design to make it fit. 1.12 Going Forward This concludes the introductory chapter. As you continue reading this book, keep in mind two things. First, the ultimate goal of digital design is to build systems that solve problems for people. While this book will give you the basic tools for design, it’s still your job to keep “the big picture” in the back of your mind. Second, cost is an important factor in every design decision; and you must ASIC design
3 Chapter 1 Introduction consider not only the cost of digital components,but also the cost of the design activity itself. Finally,as you get deeper into the text,if you encounter something that you think you've seen before but don't remember where,please consult the index. I've tried to make it as helpful and complete as possible. Drill Problems 1.1 Suggest some better-looking chapter-opening artwork to put on page 1 of the next edition of this book. 12 Give three different definitions for the word"bit"as used in this chapter. 1.3 Define the following acronyms:ASIC.CAD.CD.CO.CPLD.DIP.DVD.FPGA. HDL,IC,IP,LSI,MCM,MSI,NRE,OK,PBX,PCB,PLD,PWB,SMT,SSI VHDL.VLSI. 1.4 Research the definitions of the following acronyms:ABEL,CMOS,JPEG, MPEG,OK,PERL,VHDL.(Is OK really an acronym?) 1.6 Draw a digital circuit consisting of a 2-input AND gate and three inverters,where an inverter is connected to each of the AND gate's inputs and its output.For each of the four possible combinations of inputs applied to the two primary inputs of thiscircuit,determine the value produced at the primary output.Is there asimpler circuit that gives the same input/output behavior? 1.7 When should you use the pin diagrams of Figure 1-5 in the schematic diagram of a circuit? 1.8 What is the relationship between"die"and"dice"? NOT COPY DO NOT COPY NOT COPY Copyright 1999 by John F.Wakerly Copying Prohibited
24 Chapter 1 Introduction DO NOT COPY DO NOT COPY DO NOT COPY DO NOT COPY DO NOT COPY DO NOT COPY DO NOT COPY DO NOT COPY DO NOT COPY Copyright © 1999 by John F. Wakerly Copying Prohibited consider not only the cost of digital components, but also the cost of the design activity itself. Finally, as you get deeper into the text, if you encounter something that you think you’ve seen before but don’t remember where, please consult the index. I’ve tried to make it as helpful and complete as possible. Drill Problems 1.1 Suggest some better-looking chapter-opening artwork to put on page 1 of the next edition of this book. 1.2 Give three different definitions for the word “bit” as used in this chapter. 1.3 Define the following acronyms: ASIC, CAD, CD, CO, CPLD, DIP, DVD, FPGA, HDL, IC, IP, LSI, MCM, MSI, NRE, OK, PBX, PCB, PLD, PWB, SMT, SSI, VHDL, VLSI. 1.4 Research the definitions of the following acronyms: ABEL, CMOS, JPEG, MPEG, OK, PERL, VHDL. (Is OK really an acronym?) 1.5 Excluding the topics in Section 1.2, list three once-analog systems that have “gone digital” since you were born. 1.6 Draw a digital circuit consisting of a 2-input AND gate and three inverters, where an inverter is connected to each of the AND gate’s inputs and its output. For each of the four possible combinations of inputs applied to the two primary inputs of this circuit, determine the value produced at the primary output. Is there a simpler circuit that gives the same input/output behavior? 1.7 When should you use the pin diagrams of Figure 1-5 in the schematic diagram of a circuit? 1.8 What is the relationship between “die” and “dice”?
c ha COPY Number Systems and Codes igital systems are built from circuits that process binary digits- 0s very few real-life problems are based on binary numbers or any numbers at all.Therefore,a digital system designer must establish some correspondence between the bina- familiar numeric quantities can be represented and manipulated in a digital system,and how nonnumeric data,events,and conditions also can be epresented The first nine sections describe binary number systems and show how addition,subtraction,multiplication,and division are performed in these systems.Sections 2.10-2.13 show how other things,such as decimal num- bers,text characters,mechanical positions,and arbitrary conditions,can be encoded using strings of binary digits. Section 2.14 introduces"n-cubes,"which provide a way to visualize the relationship between different bit strings. The n-cubes are especially useful in the study oferror-detecting codes in Section 2.15.We conclude the chapter with an introduction to codes for transmitting and storing data one bit at a time : Copyright 1999 by John F.Wakerly Copying Prohibited 21
DO NOT COPY DO NOT COPY DO NOT COPY DO NOT COPY DO NOT • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • Copyright © 1999 by John F. Wakerly Copying Prohibited 21 chapter 2 Number Systems and Codes igital systems are built from circuits that process binary digits— 0s and 1s—yet very few real-life problems are based on binary numbers or any numbers at all. Therefore, a digital system designer must establish some correspondence between the binary digits processed by digital circuits and real-life numbers, events, and conditions. The purpose of this chapter is to show you how familiar numeric quantities can be represented and manipulated in a digital system, and how nonnumeric data, events, and conditions also can be represented. The first nine sections describe binary number systems and show how addition, subtraction, multiplication, and division are performed in these systems. Sections 2.10–2.13 show how other things, such as decimal numbers, text characters, mechanical positions, and arbitrary conditions, can be encoded using strings of binary digits. Section 2.14 introduces “n-cubes,” which provide a way to visualize the relationship between different bit strings. The n-cubes are especially useful in the study of error-detecting codes in Section 2.15. We conclude the chapter with an introduction to codes for transmitting and storing data one bit at a time. D