esTc 设计中心 middle vhd ENTITY middle s GENERIC(n: POSITIVE); PORT(input IN BIT; output: OUT BIT); END middle ARCHITECTURE Struc OF middle s COMPoNENT bottom iny PORT(in1: IN BIT; out1: OUT BIT) END COMPONENT SIGNAL S: BIT_VECTOR(1 TO n-1);
设计中心 ENTITY middle IS GENERIC (n : POSITIVE); PORT(input : IN BIT; output : OUT BIT); END middle; ARCHITECTURE struc OF middle IS COMPONENT bottom_inv PORT (in1 : IN BIT; out1 : OUT BIT); END COMPONENT; SIGNAL s : BIT_VECTOR(1 TO n-1); middle.VHD
esTc 设计中 BEGIN g1: FOR i IN 1 TO n GENERATE 2:Fi=1 GENERATE u1: bottom inv PORT MAP (input, s(; END GENERATE g3: IF i>1 AND i<n GENERATE u2: bottom_inv PORT MAP (s(i-1), s(D); END GENERATE g4: Fi=n GENERATE u3: bottom inv PORT MAP(s(n-1), output) END GENERATE END GENERATE I END struc
设计中心 BEGIN g1 : FOR i IN 1 TO n GENERATE g2 : IF i = 1 GENERATE u1 : bottom_inv PORT MAP (input, s(i)); END GENERATE; g3 : IF i>1 AND i<n GENERATE u2 : bottom_inv PORT MAP (s(i-1), s(i)); END GENERATE; g4 : IF i = n GENERATE u3 : bottom_inv PORT MAP (s(n-1), output); END GENERATE; END GENERATE; END struc;