esTc 设计中 Component Declaration and Instantiation Next-level of hierarchy design must have a Component Declaration for a lower-level design before it can be Instantiated ARCHITETURE structure view OF Full adder Is CoMPONENT half adder PORT(a, b: IN BIT; S, C: OUT BIT) END COMPONENT SIGNAL a b c BIT BEGIN u1: half adder PORT MAP(X,y, a, b) END structure_view
设计中心 Component Declaration and Instantiation • Next-level of hierarchy design must have a Component Declaration for a lower-level design before it can be Instantiated ARCHITETURE structure_view OF Full_adder IS COMPONENT half_adder PORT (a, b : IN BIT ;s ,c : OUT BIT); END COMPONENT; SIGNAL a,b,c:BIT; BEGIN u1: half_adder PORT MAP (x,y,a,b); …… END structure_view;
esTc 设计中 Benefits of Hierarchical Designing 1. In a design group, each designer can create separate functions(components)in separate design files. 2. These components can be shared by other designers or can be used for future projects 3. Therefore, designing hierarchically can make designs more modular and portable 4. Designing Hierarchically can also allow easier and faster alternative implementations
设计中心 Benefits of Hierarchical Designing 1. In a design group, each designer can create separate functions (components) in separate design files. 2. These components can be shared by other designers or can be used for future projects. 3. Therefore, designing hierarchically can make designs more modular and portable 4. Designing Hierarchically can also allow easier and faster alternative implementations
esTc 设计中 Example of hierarchical desian top. VHD middle vhd bottom inV VHD
设计中心 Example of hierarchical design bottom_inv.VHD middle.VHD top.VHD
esTc 设计中 ENTITY top心stop.HD END top ARCHITECTURE struc OF top Is COMPONENT middle GENER(n: POSITIVE万 PORT(input: IN BIT; output OUT BIT END COMPONENT. SIGNAL S1S2. BIT 标点符号 BEGIN U1: middle GENERIC MAP(n=>9) PORT MAP (input=>s1, output=>s2) END struc
设计中心 ENTITY top IS END top; ARCHITECTURE struc OF top IS COMPONENT middle GENERIC ( n : POSITIVE ); PORT(input : IN BIT; output : OUT BIT ); END COMPONENT; SIGNAL s1,s2 : BIT ; BEGIN U1: middle GENERIC MAP (n=>9) PORT MAP (input=>s1, output=>s2); END struc; top.VHD 标点符号
esTc 设计中 Example of hierarchical desian top. VHD middle vHD bottom inV VHD
设计中心 Example of hierarchical design bottom_inv.VHD middle.VHD top.VHD