VHDL vs.Verilog Mark Zwolinaki Digital System Design with DIGITAL LOGIC SystemVerilog with VHDL Design Digital Digital System Design with Logic VHDL with Verilog Design Second Edition Digital Systems Design Using Mark Zwolinski Stephen Brown VERILOG tephen Brown Zvonko Vranesic Digital Systems Design FPGA PROTOTYPING BY Using VHDL FPGA PROTOTYPING BY VERILOG EXAMPLES VHDL EXAMPLES XIL1HX5PA果TAN-3VER5I⊙N XLN发PARTAN-VERSION PONG P CHU Cherles H.R汽h Liry Koian Joha PONG P CHU 2021/1/13 ASIC Design,by Yan Bo 13
ASIC Design, by Yan Bo 13 VHDL vs. Verilog 2021/1/13
Topic2:FPGA Design with Verilog FPGA Design Method Design flow tools Deign Model of Verilog HDL Design style of Verilog HDL Design Examples 。RTL level design Components of Datapath Components of Controller Supplementary 。Synthesizable 。Some experiences 。Other syntax rules 2021/1/13 ASIC Design,by Yan Bo 14
ASIC Design, by Yan Bo Topic2： FPGA Design with Verilog FPGA Design Method Design flow & tools Deign Model of Verilog HDL Design style of Verilog HDL Design Examples • RTL level design • Components of Datapath • Components of Controller Supplementary • Synthesizable • Some experiences • Other syntax rules 2021/1/13 14
Basic Verilog Modeling module is a most basic building block of a design. port declarations describes the interface of the component,i.e. input and output ports. circuit functionality describes an implementation of the corresponding module. port mode port namel; module module_name(port_name1,_port_name2,. port mode port name2; 44年4年 port declarations wire interconnect namel; wire interconnect namel; Interconnect declarations assign statements; circuit functionality always @(sensitive signals list) begin endmodule functionality code end ASIC Design,by Yan Bo 15
ASIC Design, by Yan Bo 15 Basic Verilog Modeling module is a most basic building block of a design. port_mode port_name1; port_mode port_name2; ………… circuit functionality describes an implementation of the corresponding module. port declarations describes the interface of the component, i.e. input and output ports. assign statements; always @(sensitive signals list) begin functionality code end module module_name (port_name1,_port_name2, …); port declarations circuit functionality endmodule Interconnect declarations wire interconnect_name1; wire interconnect_name1; …………
Fundamental rules of Verilog module name module ports module Multiplexerc (w,a,b,s) output wi Port and inter- input a,b,si connect signal wire reserved assign m=a+h■ Continuous Assignment words statement is used if the lowercase Semicolon always @(a,b,s) unit is simple begin if (s)b; Procedural Block(always) statement with sensitivity list is else w =m used when the unit is too complex end No Semicolon endmodule 2021/1/13 ASIC Design,by Yan Bo 16
ASIC Design, by Yan Bo module MultiplexerC (w，a, b, s); output w; input a，b，s; wire m; assign m = a+b; always @(a, b, s) begin if (s) w = b; else w = m; end endmodule 16 Fundamental rules of Verilog module name reserved words lowercase 2021/1/13 Semicolon No Semicolon Continuous Assignment statement is used if the unit is simple Procedural Block(always) statement with sensitivity list is used when the unit is too complex Port and interconnect signal module ports
Basic VHDL Modeling Design Entity is a most basic building block of a design. Entity Declaration describes the interface of the component,i.e.input and output ports. Architecture describes an implementation of the corresponding module. design entity ENTITY entity name IS PORT (port name:port mode signal_type; entity declaration 444444: )； END entity name; architecture I ■■■■■■■ ARCHITECTURE architecture name OF entity name IS architecture 2 declarations ■■■■■■■■ BEGIN code architecture 3 END architecture name; January 2006 ASIC Design,by Yan Bo 17
January 2006 ASIC Design, by Yan Bo 17 Basic VHDL Modeling entity declaration architecture 1 architecture 2 architecture 3 design entity Design Entity is a most basic building block of a design. ENTITY entity_name IS PORT (port_name: port_mode signal_type; …………. ); END entity_name; Architecture describes an implementation of the corresponding module. Entity Declaration describes the interface of the component, i.e. input and output ports. ARCHITECTURE architecture_name OF entity_name IS [ declarations ] BEGIN code END architecture_name;