Moore机设计:例2 proces( clk rst-状态转移关系 begin if rst=' then st<=s0;-异步复位 elsif clkevent and clk='I'then-)时钟边沿判断 case st is when s0=>if id=x then st<=s1; else st<=s0; end if: when sl=> st<=s2 when s2=> if id=x"7then st<=s3; end if;
process(clk,rst) --状态转移关系 begin if rst='1' then st<=s0; --异步复位 elsif clk'event and clk='1' then --时钟边沿判断 case st is when s0=> if id=x"3" then st<=s1; else st<=s0; end if; when s1=> st<=s2; when s2=> if id=x"7" then st<=s3; end if; Moore机设计：例2
Moore机设计:例2 when s3=> if id=x"7 then st<=s0; elsif id=xg then st<=s 4 end if: when s4=> if id=xb" then st<=so: end if; when others=>st<=so end case; end if: end process, y<=st(1 downto0);-输出方程 end beh:
when s3=> if id=x"7" then st<=s0; elsif id=x"9" then st<=s4; end if; when s4=> if id=x"b" then st<=s0; end if; when others=>st<=s0; end case; end if; end process; y<=st(1 downto 0); --输出方程 end beh; Moore机设计：例2
Moore机设计:例3 例3简单状态机设计(教材7.4/9.2.1) state machine 初始态:z=0 A B 连续2个触发沿A=1,则 z=1 若z=1且b=1,则z保持1
例3 简单状态机设计( 教材7.4 /9.2.1) 初始态：z=0 连续2个触发沿A=1，则 z=1; 若z=1且b=1, 则z保持1。 Moore机设计：例3
Moore机设计:例3 例3简单状态机设计(教材7.4/9.2.1) a0 A okO/z A AB init AA AB A'B A'B a 1 ok1/z A
例3 简单状态机设计( 教材7.4 /9.2.1) Moore机设计：例3
Moore机设计:例3 architecture beh of smexamp is type sreg type is(init, a0, al, ok0, okD); signal sreg: sreg type begin process(clk begin if clk'event and clke"l then case sreg Is when init=> if a=0 then sreg<=a0; elsif a= then sreg<=al; end if:
architecture beh of smexamp is type sreg_type is (init,a0,a1,ok0,ok1); signal sreg:sreg_type; begin process(clk) begin if clk'event and clk='1' then case sreg is when init => if a='0' then sreg<=a0; elsif a='1' then sreg<=a1; end if; Moore机设计：例3