Patterning materials at the nanoscale 6.12J/3.155J Microelectronic processing Outline 1. Introduction- How small would you like to go?... can you go 2. Optical and other lithography 3. Subtractive and additive patterning 4. More exotic patterning methods: Interference (Imprint,) Block copolymers elf asse (Building on last years notes of Caroline ross) Dec.10,2003
D e c. 10 , 2 0 0 3 6.12J / 3.155J Microelectronic processing Patterning materials at the nanoscale Outline 1. Introduction - How small would you like to go?… can you go? 2. Optical and other lithography 3. Subtractive and additive patterning 4. More exotic patterning methods: Interference, (Imprint,) Block copolymers Self assembly (Building on last year’s notes of Caroline Ross)
How small would you like to go?...and can you go? with semiconductors?. with lithography 6.12J/3.155J Microelectronic processing Semiconductor scaling drivers: Speed of light in global interconnects, vac/vK Increased information density ◆ Increased logic speed ◆ Economies of scale Semiconductor scaling challenges diffusion length control, statistics, especially for channe Thermal management, V2/R Power density: Pentium: Pentium Il Pentium Il: Nuclear Reactor Dielectric breakdown field, vd ◆ Interconnect cross-talk, delay,C↓,T=LC Information stability: kBT< CV2 Screening lengths(range of band bending, depletion regions Dec.10,2003
D e c. 10 , 2 0 0 3 6.12J / 3.155J Microelectronic processing How small would you like to go? …and can you go? with semiconductors?…with lithography? Semiconductor scaling drivers: w Speed of light in global interconnects, v µ c/√k w Increased information density w Increased logic speed w Economies of scale Semiconductor scaling challenges: w diffusion length control, statistics, especially for channel w Thermal management, V 2/R Power density: Pentium: Pentium III :: Pentium III: Nuclear Reactor w Dielectric breakdown field, V/d w Interconnect cross-talk, delay, CØ , t = L/C w Information stability: kBT < CV 2 w Screening lengths (range of band bending, depletion regions)
How small can MOSFETs go? 6.12J/3.155J Microelectronic processing 10 Four problems as size shrinks 1. Drai doping concentration Gate le ng th limited by thermodynamics 导 2. Physical tunnel through gate oxide (lot< lon) 01 3. Statistical fluctuations Junction depth of doping: Nd s 50/ (10 nm)3 ate 0.0 Oxide thic kness source 1970 1980 1990 2000 201[ Year Dec.10,2003
D e c. 10 , 2 0 0 3 6.12J / 3.155J Microelectronic processing Four problems as size shrinks: 1. Drain, source doping concentration limited by thermodynamics 2. Physical tunneling through gate oxide (Ioff < Ion) 3. Statistical fluctuations of doping: Nd ≈ 50/(10 nm)3 4. Economic cost of Fab How small can MOSFETs go?
International Technology roadmap for Semiconductors: 2002 6.12J/3. 155J Microelectronic processing YEAR OF PRODUCTION200120021203204205120012007 DRAM Pitch (m)130 115 100 0 80 70 65 MPU为 Pitch(nn 1301079080 MPUPrinted Gate Length(n) 75655345 4 35 MPU Physical Gate Length (en) 534537322825 YEAR OFPRODUCTION 201020132016 DRAM Pitch (nm) 453222 MPU Pitch (* y 4532|22 MPU Printed Gate Length(nm) 251813 MPU Physical Gate Length(/w) 18139 N≈50n10×10×10m3 Dec.10,2003
D e c. 10 , 2 0 0 3 6.12J / 3.155J Microelectronic processing International Technology Roadmap for Semiconductors; 2002 Nd ≈ 50 in 10x10x10 nm3
How small can you go with semiconductors?. with lithography? 6.12J/3.155J Microelectronic processing Lithography limitations fresnel and fraunhoffer limitations other light sources or particles? When the optical resolution exceeds physical resolution e-beam, secondary generation blurs lines Particle dama Dec.10,2003
D e c. 10 , 2 0 0 3 6.12J / 3.155J Microelectronic processing How small can you go with semiconductors?…with lithography? Lithography limitations: w Fresnel and Fraunhoffer limitations w Other light sources or particles? w When the optical resolution exceeds physical resolution w e-beam, secondary generation blurs lines w Particle damage