3.155J/6.152JFal2003 CAP Massachusetts Institute of Technology POLY GATE MOSCAP PROCESS SUMMARY Lab session 1 1. 1 Lab Safety and Cleanroom Orientation 1.2 RCA ( ICL RC 1.3 Gate Oxidation Thermco Atmospheric Furnace(5D-FieldOx 1.4 Doped Polysilicon Deposition Thermco LPCVD(6A-Poly) 1.5 Anneal Thermco Atmospheric Furnace(5B-Anneal) Lab session 2 2. 1 Measure oxide and polysilicon thickness(UV1280 2.2 Etch oxide in BOE until de-wet (OxEtch-BOE) 2.3 HMDS, Photoresist Application, Postbake(SSI coater track) 2.4 Dry etch backside polysilicon( LAM490B) 2.5 Etch backside oxide in BOE until de-wet(OXEtch-BOE 2.6 Strip frontside resist with Matrix System One Stripper(Asher) ab session 3 3.1 HMDS, Photoresist Application, Pre-bake(SSI coater track 3.2 Exposure, Development, and Inspection(i-stepper), (SSl coater track),(optical microscope 3.3 Dry-etch polysilicon(LAM490B) 3. 4 Strip photoresist with Matrix System One Stripper(Asher) Testing T1 Device characterization: MOS Capacitor Determine oxide capacitance. Determine bulk dopant concentration Determine fixed interface charge T2 Sheet resistance measurement: Van der Pauw structure
3.155J / 6.152J Fall 2003 MOSCAP 1 Massachusetts Institute of Technology POLY GATE MOSCAP PROCESS SUMMARY Lab Session 1 1.1 Lab Safety and Cleanroom Orientation 1.2 RCA (ICL RCA) 1.3 Gate Oxidation Thermco Atmospheric Furnace (5D-FieldOx) 1.4 Doped Polysilicon Deposition Thermco LPCVD (6A-Poly) 1.5 Anneal Thermco Atmospheric Furnace (5B-Anneal) Lab Session 2 2.1 Measure oxide and polysilicon thickness (UV1280) 2.2 Etch oxide in BOE until de-wet (OxEtch-BOE) 2.3 HMDS, Photoresist Application, Postbake (SSI coater track) 2.4 Dry etch backside polysilicon (LAM490B) 2.5 Etch backside oxide in BOE until de-wet (OxEtch-BOE) 2.6 Strip frontside resist with Matrix System One Stripper (Asher) Lab Session 3 3.1 HMDS, Photoresist Application, Pre-bake (SSI coater track) 3.2 Exposure, Development, and Inspection (i-stepper), (SSI coater track), (optical microscope) 3.3 Dry-etch polysilicon (LAM490B) 3.4 Strip photoresist with Matrix System One Stripper (Asher) Testing T.1 Device characterization: MOS Capacitor Determine oxide capacitance. Determine bulk dopant concentration. Determine fixed interface charge. T.2 Sheet resistance measurement: Van der Pauw structure
3.155J/6.152 J Fall2003 MOSCAP MOSCAP LAB SESSION Gate Oxidation, Polysilicon Deposition and Anneal Location: ICL (2 floor, Building 39) Overview of lab session This first session will start with and introduction to the Integrated Circuits Lab(ICL) lab environment, as well as proper and safe working practices. The fabrication sequence will begin with a rigorous cleaning procedure that eliminates sources of wafer contamination and preserves the clean integrity of the furnaces. a-500 a gate oxide will be grown using a dry oxidation process. Immediately following the oxidation, the doped polysilicon gate layer will be deposited by chemical vapor deposition( LPCVD )to a target thickness of 2500 A. The deposited polysilicon ayer will be annealed to enhance an even distribution of dopants Lab objectives Review of lab safety and administrative procedures Introduction to cleanroom gowning and wafer-handling practices to avoid contamination Characterize basic physical and electrical characteristics of the starting n-type silicon substrates Complete growth and characterization of the gate oxide Complete growth of the gate polysilicon Instruction on the following major pieces of lab equipment Semifab RCA Cleaning Station Thermco Atmospheric Furnace(5D-FieldOx) Thermco Low Pressure Furnace(6A-Poly) Thermco Atmospheric Furnace(5B-anneal) Before attending this lab session, make sure to read the Standard Operating Procedures for the above equipment. SOPs can be accessed at http://www-mtl.mitedu/mtihome/3mfab/soP.html Lab procedures: 1. Lab Safety and Cleanroom Orientation Read the sections on lab safety and code of conduct before attending lab session 2. RCA Wafer Clean Follow the SOP for the Semifab RCA Cleaning Station 3. Gate Oxidation Note: This step must be immediately preceded by RCa clean Approximately 500 A will be grown using a dry oxidation process at 1000 C. Follow the SOP for the Thermo Atmospheric Furnace(5D-FieldOx) using recipe 6. 152 GATEOX 500A"with an interval time of 1 hour for the step of dry oxidation 4. Doped Polysilicon Deposition Note: this step must immediately follow the gate oxidation About 2500 A of phosphorus-doped polysilicon will be deposited by LPCVD in the Thermco Furnace(6A-Poly) The deposition rate is fixed at -30 A/min 5. Anneal The deposited polysilicon gate layer will be annealed at 950C for 12 minutes in a nitrogen ambient to enhance an even distribution of phosphorus dopants. Follow the SOP for the Thermo Atmospheric Furnace(5B-anneal)
3.155J / 6.152J Fall 2003 MOSCAP 2 MOSCAP LAB SESSION 1 Gate Oxidation, Polysilicon Deposition and Anneal Location: ICL (2nd floor, Building 39) Overview of Lab Session: This first session will start with and introduction to the Integrated Circuits Lab (ICL) lab environment, as well as proper and safe working practices. The fabrication sequence will begin with a rigorous cleaning procedure that eliminates sources of wafer contamination and preserves the clean integrity of the furnaces. A ~500 Å gate oxide will be grown using a dry oxidation process. Immediately following the oxidation, the doped polysilicon gate layer will be deposited by chemical vapor deposition (LPCVD) to a target thickness of 2500 Å. The deposited polysilicon layer will be annealed to enhance an even distribution of dopants. Lab Objectives: • Review of lab safety and administrative procedures • Introduction to cleanroom gowning and wafer-handling practices to avoid contamination • Characterize basic physical and electrical characteristics of the starting n-type silicon substrates • Complete growth and characterization of the gate oxide • Complete growth of the gate polysilicon • Instruction on the following major pieces of lab equipment: • Semifab RCA Cleaning Station • Thermco Atmospheric Furnace (5D-FieldOx) • Thermco Low Pressure Furnace (6A-Poly) • Thermco Atmospheric Furnace (5B-anneal) Before attending this lab session, make sure to read the Standard Operating Procedures for the above equipment. SOPs can be accessed at: http://www-mtl.mit.edu/mtlhome/3Mfab/sop.html Lab Procedures: 1. Lab Safety and Cleanroom Orientation Read the sections on lab safety and code of conduct before attending lab session. 2. RCA Wafer Clean Follow the SOP for the Semifab RCA Cleaning Station. 3. Gate Oxidation Note: This step must be immediately preceded by RCA clean! Approximately 500 Å will be grown using a dry oxidation process at 1000 C. Follow the SOP for the Thermco Atmospheric Furnace (5D-FieldOx) using recipe "6.152 GATEOX 500A" with an interval time of 1 hour for the step of dry oxidation. 4. Doped Polysilicon Deposition Note: this step must immediately follow the gate oxidation. About 2500 Å of phosphorus-doped polysilicon will be deposited by LPCVD in the Thermco Furnace (6A-Poly). The deposition rate is fixed at ~30 A/min. 5. Anneal The deposited polysilicon gate layer will be annealed at 9500 C for 12 minutes in a nitrogen ambient to enhance an even distribution of phosphorus dopants. Follow the SOP for the Thermco Atmospheric Furnace (5B-anneal)
3.155J/6.152 J Fall2003 MOSCAP Pre-Lab Questions 1. What contaminants does the rCa clean remove? What is the purpose of the HF dip in the rca clean? 2. Why is dry oxidation used to grow the gate oxide? 3. From the oxide growth chart in the Appendix, predict the gate oxide thickness after the oxidation 4. From the oxide color chart in the Appendix, what color would one expect the gate oxide to appear 5. What are the advantages of using polysilicon rather than aluminum for the gate electrode? 6. What is the by-product of the polysilicon deposition? What controls the deposition rate (transfer of SiH4, reaction at the surface of the substrate, or removal of the by-product)? 7. Sketch a cross section of the wafer after this lab session
3.155J / 6.152J Fall 2003 MOSCAP 3 Pre-Lab Questions: 1. What contaminants does the RCA clean remove? What is the purpose of the HF dip in the RCA clean? 2. Why is dry oxidation used to grow the gate oxide? 3. From the oxide growth chart in the Appendix, predict the gate oxide thickness after the oxidation. 4. From the oxide color chart in the Appendix, what color would one expect the gate oxide to appear? 5. What are the advantages of using polysilicon rather than aluminum for the gate electrode? 6. What is the by-product of the polysilicon deposition? What controls the deposition rate (transfer of SiH4, reaction at the surface of the substrate, or removal of the by-product)? 7. Sketch a cross section of the wafer after this lab session
3.155J/6.152 J Fall2003 MOSCAP MOSCAP LAB SESSION 2 Back-side Strip Location: ICL (2 floor, Building 39) Overview of lab session The first step of this lab session will be to characterize the oxide and polysilicon films deposited in lab session 1. The main processing taking place in this lab session will be the removal of the oxide and polysilicon layers from the back side of the wafers. This will allow electrical contact to the back side of the wafer. The wafers will be coated with a photoresist solution using an automatic coating system which has several modules operating in a pipelined fashion. The first module treats each wafer with Hexamethyldisilazane(HMDs)vapor, an adhesion promoter. Next, a photoresist solution is dispensed onto the wafer and evenly distributed by a spin-on technique Finally, the wafer is baked to expel solvents from the photoresist. Since the wafers will not be patterned photolithographically, the wafers will be post-baked directly(rather than pre-baked exposed, and then post-baked) to harden the resist into a protective masking layer. The back sides of the wafers will be etched dry-etched in He/Cl2 plasma. Next, the oxide will be wet-etched in buffered oxide etch(BOE), a solution of hydrofluoric acid. Finally, the photoresist will be stripped by oxygen plasma etch Lab Objectives: Complete characterization of Oxide and Polysilicon films grown in Lab Session 1 Remove oxide and polysilicon films from back side of wafers Instruction on the following pieces of lab equipment KLA Tencor UV1280 Film Thickness Measurement System SSI Coater Track LAM 490B Plasma Etcher Oxide etch sink Matrix 106 System One Stripper Before attending this lab session, make sure to read the Standard Operating Procedures for the above equipment. SOPs can be accessed at: http://www-mtl.mitedu/mtlhome/3mfab/sop.html Lab procedure 1. Characterize Oxide and Polysilicon deposited in Lab session 1 Measure the oxide and polysilicon thickness using the UV1280 Note: An oxide color chart is enclosed in the Appendix. The color chart assumes perpendicular illumination and viewing of wafer surface under white fluorescent lighting 2. Etch oxide in boe (Oxide etch sink Using the Oxide Etch Sink, etch the native oxide on the polisilicon surface of the wafer in Buffered-Oxide-Etch(BOE). The etch rate for bOE is about 1000 A/min the thickness of the native oxide is around 200 a so estimate the approximate etch time required. When the BOE etch is complete, the BOE should'de-wet'or bead up off the wafer. After completing etch, rinse thoroughly with DI water and spin dry Overall reaction for etching Sio2 with BOE SiO2+ 6HF == H2+ SiF6+ 2H2O where a buffering agent, ammonium fluoride(NH4 F), is added to maintain HF concentration and to control pH to minimize photoresist attack) NH4F <== NH3 HF
3.155J / 6.152J Fall 2003 MOSCAP 4 MOSCAP LAB SESSION 2 Back-side Strip Location: ICL (2nd floor, Building 39) Overview of Lab Session: The first step of this lab session will be to characterize the oxide and polysilicon films deposited in lab session 1. The main processing taking place in this lab session will be the removal of the oxide and polysilicon layers from the back side of the wafers. This will allow electrical contact to the back side of the wafer. The wafers will be coated with a photoresist solution using an automatic coating system which has several modules operating in a pipelined fashion. The first module treats each wafer with Hexamethyldisilazane (HMDS) vapor, an adhesion promoter. Next, a photoresist solution is dispensed onto the wafer and evenly distributed by a spin-on technique. Finally, the wafer is baked to expel solvents from the photoresist. Since the wafers will not be patterned photolithographically, the wafers will be post-baked directly (rather than pre-baked, exposed, and then post-baked) to harden the resist into a protective masking layer. The back sides of the wafers will be etched dry-etched in He/Cl2 plasma. Next, the oxide will be wet-etched in buffered oxide etch (BOE), a solution of hydrofluoric acid. Finally, the photoresist will be stripped by oxygen plasma etch. Lab Objectives: • Complete characterization of Oxide and Polysilicon films grown in Lab Session 1. • Remove oxide and polysilicon films from back side of wafers. • Instruction on the following pieces of lab equipment • KLA Tencor UV1280 Film Thickness Measurement System • SSI Coater Track • LAM 490B Plasma Etcher • Oxide Etch Sink • Matrix 106 System One Stripper Before attending this lab session, make sure to read the Standard Operating Procedures for the above equipment. SOPs can be accessed at: http://www-mtl.mit.edu/mtlhome/3Mfab/sop.html Lab Procedures: 1. Characterize Oxide and Polysilicon deposited in Lab session 1. Measure the oxide and polysilicon thickness using the UV1280. Note: An oxide color chart is enclosed in the Appendix. The color chart assumes perpendicular illumination and viewing of wafer surface under white fluorescent lighting. 2. Etch oxide in BOE. (Oxide etch sink) Using the Oxide Etch Sink, etch the native oxide on the polisilicon surface of the wafer in Buffered-Oxide-Etch (BOE). The etch rate for BOE is about 1000 Å/min. The thickness of the native oxide is around 200 Å so estimate the approximate etch time required. When the BOE etch is complete, the BOE should ‘de-wet’ or bead up off the wafer. After completing etch, rinse thoroughly with DI water and spin dry. Overall reaction for etching SiO2 with BOE: SiO2 + 6HF ==> H2 + SiF6 + 2H2O where a buffering agent, ammonium fluoride (NH4F), is added to maintain HF concentration and to control pH (to minimize photoresist attack): NH4F <==> NH3 + HF
3.155J/6.152 J Fall2003 CAP NOTE: BOE contains a high concentration of hydrofluoric acid(HF). Be aware of the angers of handling HF! 3. Coat frontside of wafers with blanket photoresist and bake Follow the SoP for the SSI Coater Track, using the following three modules HMDS module: treatment promotes adhesion of photoresist coating module: photoresist will be dispensed and spun on for -1 micron thickness bake module: at 95C for 60 s on hot plate 4. Dry-etch backside polysilicon in He/Cl2 plasma Use the LAM 490B with recipe"BACKSIDE POLY (5KA)"to etch the exposed polysilicon on the backside of the wafer. The wafers will be loaded into the machine upside down Take care handling the wafers to avoid marring the front side Based on you previous measurements of polysilicon thickness, estimate the appropriate etch time required 5. Etch backside gate oxide in BOE until de-wet (Oxide etch sink) Using the Oxide Etch Sink, etch the exposed oxide on the back side of the wafer in Buffered-Oxide-Etch(BOE). The etch rate for BOE is about 1000 A/min. Based on your previous measurements of oxide thickness, estimate the approximate etch time required When the boe etch is complete, the boE should'de-wet or bead up off the wafer. After completing etch, rinse thoroughly with DI water and spin dry NOTE: BOE contains a high concentration of hydrofluoric acid(HF). Be aware of the dangers of handling HF 6. Strip photoresist with the Matrix System One Stripper(Asher) This is an oxygen plasma etch Pre-lab questions 1. Why is HMDS applied to the wafers before photoresist application? 2. Why is BOE particularly dangerous? How should one be gowned when handling BOE? 3. What is the purpose of Hgf in BOE? 4. Sketch a cross-section of the wafer after the processing in this session
3.155J / 6.152J Fall 2003 MOSCAP 5 NOTE: BOE contains a high concentration of hydrofluoric acid (HF). Be aware of the dangers of handling HF! 3. Coat frontside of wafers with blanket photoresist and bake. Follow the SOP for the SSI Coater Track, using the following three modules • HMDS module: treatment promotes adhesion of photoresist • coating module: photoresist will be dispensed and spun on for ~1 micron thickness • bake module: at 95 C for 60 s on hot plate 4. Dry-etch backside polysilicon in He/Cl2 plasma. Use the LAM 490B with recipe "BACKSIDE POLY (5KA)" to etch the exposed polysilicon on the backside of the wafer. The wafers will be loaded into the machine upside down. Take care handling the wafers to avoid marring the front side. Based on you previous measurements of polysilicon thickness, estimate the appropriate etch time required. 5. Etch backside gate oxide in BOE until de-wet. (Oxide etch sink) Using the Oxide Etch Sink, etch the exposed oxide on the back side of the wafer in Buffered-Oxide-Etch (BOE). The etch rate for BOE is about 1000 Å/min. Based on your previous measurements of oxide thickness, estimate the approximate etch time required. When the BOE etch is complete, the BOE should ‘de-wet’ or bead up off the wafer. After completing etch, rinse thoroughly with DI water and spin dry. NOTE: BOE contains a high concentration of hydrofluoric acid (HF). Be aware of the dangers of handling HF! 6. Strip photoresist with the Matrix System One Stripper (Asher) This is an oxygen plasma etch. Pre-lab questions: 1. Why is HMDS applied to the wafers before photoresist application? 2. Why is BOE particularly dangerous? How should one be gowned when handling BOE? 3. What is the purpose of NH4F in BOE? 4. Sketch a cross-section of the wafer after the processing in this session