DAaba DS12887 Real Time Clock www.dalsemi.com FEATURES PIN ASSIGNMENT Drop-in replacement for IBM AT computer clock/calendar Pin-compatible with the MC146818B and DS1287 MOT Totally nonvolatile with over 10 years of omeymcethu. 24 NC quartz.and support circuitry ■Counts seco Is minutes hours days day of AD3 RESE the week.date.month.and ear with leap AD4 R representation of time, 14 AS GND12 13■c 1 ur clock with AM and PM in 24-PIN ENCAPSULATED PACKAGE Selectable between Motorola and Intel bus PIN DESCRIPTION Multiplex bus for pin efficiency AD7 .Interfaced with software as 128 RAM Multiplexed Address/Data Bus locations lection 14 bytes of clock and control registers Cs 114 bytes of general purpose RAM -Chip Select .Programmable square wave output signal AS -Address Strobe compatible interrupt signals(RQ) R/W -Read/Write Input DS Data Strobe interrupts are separately software- maskable and testable RESET -Reset Input Time-of-day alarm once/second to IRO -Interrupt Request Output once/day SOW -Square Wave Output Periodic rates from 122 ms to 500 ms -+5 Volt Supply End of clock update cycle GND -Ground DESCRIPTION DS12887 Real Time Clock plus RAM is designed to be a direct replacement for the DS1287.Th D17is identical in fom,it and tunction to the DS1287,and has anaddtonal64bytes of general purpose RAM.Access to this additional RAM space is determined by the logic level presented on AD6 during the address portion of an access cycle.A lithium energy source,quartz crystal,and write- protection circuitry are contained within a 24-pin dual in-line package.As such,the DS12887 is a complete subsystem replacing 16 components in a typical application.The functions include a nonvolatile time-of day clock,an alarm,a one-hundred-year calendar,programmable interrupt,square wave 1of19 110899
1 of 19 110899 FEATURES ß Drop–in replacement for IBM AT computer clock/calendar ß Pin-compatible with the MC146818B and DS1287 ß Totally nonvolatile with over 10 years of operation in the absence of power ß Self–contained subsystem includes lithium, quartz, and support circuitry ß Counts seconds, minutes, hours, days, day of the week, date, month, and year with leap year compensation valid up to 2100 ß Binary or BCD representation of time, calendar, and alarm ß 12– or 24–hour clock with AM and PM in 12–hour mode ß Daylight Savings Time option ß Selectable between Motorola and Intel bus timing ß Multiplex bus for pin efficiency ß Interfaced with software as 128 RAM locations – 14 bytes of clock and control registers – 114 bytes of general purpose RAM ß Programmable square wave output signal ß Bus–compatible interrupt signals ( IRQ ) ß Three interrupts are separately software– maskable and testable – Time–of–day alarm once/second to once/day – Periodic rates from 122 ms to 500 ms – End of clock update cycle PIN ASSIGNMENT PIN DESCRIPTION AD0–AD7 – Multiplexed Address/Data Bus NC – No Connection MOT – Bus Type Selection CS – Chip Select AS – Address Strobe R/ W – Read/Write Input DS – Data Strobe RESET – Reset Input IRQ – Interrupt Request Output SQW – Square Wave Output VCC – +5 Volt Supply GND – Ground DESCRIPTION The DS12887 Real Time Clock plus RAM is designed to be a direct replacement for the DS1287. The DS12887 is identical in form, fit, and function to the DS1287, and has an additional 64 bytes of general purpose RAM. Access to this additional RAM space is determined by the logic level presented on AD6 during the address portion of an access cycle. A lithium energy source, quartz crystal, and write– protection circuitry are contained within a 24–pin dual in-line package. As such, the DS12887 is a complete subsystem replacing 16 components in a typical application. The functions include a nonvolatile time–of–day clock, an alarm, a one-hundred–year calendar, programmable interrupt, square wave NC DS12887 Real Time Clock www.dalsemi.com
DS12887 .and 11 by e of nonvolatile static RAM.The real time clock is distinctive in that time-of day and memory are maintained even in the absence of power OPERATION The block diagram in Figure 1 shows the pin connections with the major internal functions of the DS12887.The following paragraphs describe the function of each pin. BLOCK DIAGRAM DS12887 Figure 1 AS POWER-DOWN/POWER-UP CONSIDERATIONS The Real Time Clock function will continue to operate and all of the RAM,time,calendar,and alarm memory locations remain nonvolatile regardless of the level of the Voc input.When Vcc is applied to the DS12887 and reaches a level of greater than 4.25 volts,the device becomes accessible after 200 ms provided that the oscillator is running and the oscillator countdown chain is not in reset(see Register A). This time period allows the system to stabilize after power is applied.When Vcc falls below 4.25 volts, slect in is inmlly forced toe the input pin state,all are ignored and al nce state kR8ne8Re资新mof nd anmeryour SIGNAL DESCRIPTIONS GND,Vcc-DC power is provided to the device on these pins.Vcc is the +5 volt input.When 5 volts are 2of19
DS12887 2 of 19 generator, and 114 bytes of nonvolatile static RAM. The real time clock is distinctive in that time–of–day and memory are maintained even in the absence of power. OPERATION The block diagram in Figure 1 shows the pin connections with the major internal functions of the DS12887. The following paragraphs describe the function of each pin. BLOCK DIAGRAM DS12887 Figure 1 POWER–DOWN/POWER–UP CONSIDERATIONS The Real Time Clock function will continue to operate and all of the RAM, time, calendar, and alarm memory locations remain nonvolatile regardless of the level of the VCC input. When VCC is applied to the DS12887 and reaches a level of greater than 4.25 volts, the device becomes accessible after 200 ms, provided that the oscillator is running and the oscillator countdown chain is not in reset (see Register A). This time period allows the system to stabilize after power is applied. When VCC falls below 4.25 volts, the chip select input is internally forced to an inactive level regardless of the value of CS at the input pin. The DS12887 is, therefore, write–protected. When the DS12887 is in a write–protected state, all inputs are ignored and all outputs are in a high impedance state. When VCC falls below a level of approximately 3 volts, the external VCC supply is switched off and an internal lithium energy source supplies power to the Real Time Clock and the RAM memory. SIGNAL DESCRIPTIONS GND, VCC – DC power is provided to the device on these pins. VCC is the +5 volt input. When 5 volts are applied within normal limits, the device is fully accessible and data can be written and read. When VCC is below 4.25 volts typical, reads and writes are inhibited. However, the timekeeping function continues
DS12887 unaffected by the lower input voltage as vc falls below 3 yolts typical the ram and timekeeper are switched over to an internal lithium y source The timekeeping function maintains an accuracy of+l minute per month at 25C regardless of the voltage input on the Voc pin. MOT (Mode Seleet)-The MOT pin offers the flexibility to choose between two bus types.When connected to Vcc,Motorola bus timing is selected.When connected to GND or left disconnected,Intel bus timing is selected.The pin has an internal pulldown resistance of approximately 20 k. SQW(Square Wave Output)-The SQW pin can output a signal from one of 13 taps provided by the 15 internal divider stages of the Real Time Clock.The frequency of the SQW pin can be changed by programming Register A as shown in Table 1.The SQW signal can be turned on and off using the SQWE bit in Register B.The SQW signal is not available when Vcc is less than 4.25 volts,typically. PERIODIC INTERRUPT RATE AND SQUARE WAVE OUTPUT FREQUENCY Table 1 SELECT BITS REGISTER A t PERIODIC SOW OUTPUT INTERRUPT RATE FREOUENCY 0 3.90625 256z 7.8125ms 28H☑ 122070u1s 8.192kHz 0 0 244141us 4.096kHz 488281μs 2048kH2 976.56254s 1.024kH亚 0 1.953125ms 512Hz 1 0 0 0 3.90625ms 256Hz 0 7.8125ms 128Hz 0 15.625ms 64 Hz 3125m 32H2 62. ms 16亚 125ms 8H☑ 250ms 4H2 500ms 2 Hz ADO-AD7 (Multiplexed Bidirectional Address/Data Bus)-Multiplexed buses save pins because address information and data information time-share the same signal paths.The addresses are present during the first portion of the bus cycle and the same pins and signal paths are used for data in the second portion of the cycle.Address/data multiplexing does not slow the access time of the DS12887 since the bus change from address to data occurs during the internal RaM access time.Addresses must be valic prior to the falling edge of AS/ALE,at which time the DS12887 latches the address from AD0 to AD6. Valid write data must be present and held stable during the latter portion of the DS or WR pulses.In a read cycle the DS12887 outputs 8 bits of data during the latter portion of the DS or RD pulses.The read cycle is terminated and the bus returns to a high impedance state as DS transitions low in the case of Motorola timing or as RD transitions high in the case of Intel timing AS(Address Strobe Input)-A positive ing address strobe pulse serves to demultiplex the bus The falling edge of AS/ALE causes the address to be latched within the DS12887.The next rising edge that 3of19
DS12887 3 of 19 unaffected by the lower input voltage. As VCC falls below 3 volts typical, the RAM and timekeeper are switched over to an internal lithium energy source. The timekeeping function maintains an accuracy of ±1 minute per month at 25°C regardless of the voltage input on the VCC pin. MOT (Mode Select) – The MOT pin offers the flexibility to choose between two bus types. When connected to VCC, Motorola bus timing is selected. When connected to GND or left disconnected, Intel bus timing is selected. The pin has an internal pulldown resistance of approximately 20 kW. SQW (Square Wave Output) – The SQW pin can output a signal from one of 13 taps provided by the 15 internal divider stages of the Real Time Clock. The frequency of the SQW pin can be changed by programming Register A as shown in Table 1. The SQW signal can be turned on and off using the SQWE bit in Register B. The SQW signal is not available when VCC is less than 4.25 volts, typically. PERIODIC INTERRUPT RATE AND SQUARE WAVE OUTPUT FREQUENCY Table 1 SELECT BITS REGISTER A RS3 RS2 RS1 RS0 tPI PERIODIC INTERRUPT RATE SQW OUTPUT FREQUENCY 0 0 0 0 None None 0 0 0 1 3.90625 ms 256 Hz 0 0 1 0 7.8125 ms 128 Hz 0 0 1 1 122.070 ms 8.192 kHz 0 1 0 0 244.141 ms 4.096 kHz 0 1 0 1 488.281 ms 2.048 kHz 0 1 1 0 976.5625 ms 1.024 kHz 0 1 1 1 1.953125 ms 512 Hz 1 0 0 0 3.90625 ms 256 Hz 1 0 0 1 7.8125 ms 128 Hz 1 0 1 0 15.625 ms 64 Hz 1 0 1 1 31.25 ms 32 Hz 1 1 0 0 62.5 ms 16 Hz 1 1 0 1 125 ms 8 Hz 1 1 1 0 250 ms 4 Hz 1 1 1 1 500 ms 2 Hz AD0–AD7 (Multiplexed Bidirectional Address/Data Bus) – Multiplexed buses save pins because address information and data information time-share the same signal paths. The addresses are present during the first portion of the bus cycle and the same pins and signal paths are used for data in the second portion of the cycle. Address/data multiplexing does not slow the access time of the DS12887 since the bus change from address to data occurs during the internal RAM access time. Addresses must be valid prior to the falling edge of AS/ ALE, at which time the DS12887 latches the address from AD0 to AD6. Valid write data must be present and held stable during the latter portion of the DS or WR pulses. In a read cycle the DS12887 outputs 8 bits of data during the latter portion of the DS or RD pulses. The read cycle is terminated and the bus returns to a high impedance state as DS transitions low in the case of Motorola timing or as RD transitions high in the case of Intel timing. AS (Address Strobe Input) – A positive-going address strobe pulse serves to demultiplex the bus. The falling edge of AS/ALE causes the address to be latched within the DS12887. The next rising edge that
DS12887 occurs on the AS bus will clear the address regardless of whether cs is asserted.Access commands should be sent in pairs. DS(Data Strobe or Read Input)-The DS/RD pin has two modes of operation depending on the level of the MOT pin.When the MOT pin is connected to Vcc.Motorola bus timing is selected.In this mode DS is a positive pulse during the latter portion of the bus cycle and is called Data Strobe.During read D signifies the time that the DS1287siv th bidirectiona busIni cles the trailin of DS ses the DS12887 to latch the written data.Wher the MOT pin is conne cted to GND,Intel bus timing is selected.In this mode the DS pin is called Read(RD).RD identifies the time period when the DS12887 drives the bus with read data.The RD signal is the same definition as the Output Enable (OE)signal on a typical memory. R/W (Read/Write Input)-The R/W pin also has two modes of operation.When the MOT pin is connected to Vc for Motorola timing.R/w is at a level which indicates whether the current cycle is a read or write.A read cycle is indicated with a high level on R/w while DS is high.A write cycle is indicated when R/W is low during DS When the MOT pin is connected to GND for Intel timing,the R/W signal is an active low signal called WR.In this mode the R/W pin has the same meaning as the Write Enable signal (WE)on generic RAMs. CS(Chip Select Input)-The Chip Select signal must be asserted low for a bus cycle in the DS12887 to be accessed.Cs must be kept in the active state during DS and AS for Motorola timing and during RD and WR for Intel timing.Bus cycles which take place without asserting cs will latch addresses but no access will occur.When Wc is below 4.25 volts,the DS12887 internally inhibits access cycles by interally disabling the Cs input.This action protects both the real time clock data and RAM data during power outages IRQ (Interrupt Request Output)-The IRQ pin is an active low output of the DS12887 that can be used as an interrupt input to a processor.The IRQ output remains low as long as the status bit causing the interrupt is present and the corresponding interrupt-enable bit is set.To clear the IRQ pin the processor program normally reads the C register.The RESET pin also clears pending interrupts. When no interrupt conditions are present,the IRQ level is in the high impedance state.Multiple interrupting devices can be connected to an IRQ bus.The IRQ bus is an open drain output and requires an external pullup resistor. RESET (Reset Input)-The RESET pin has no effect on the clock,calendar,or RAM.On power-up the RESET pin can be held low for a time in order to allow the power supply to stabilize.The amount of time that RESET is held low is dependent on the application.However,if RESET is used on power-up,the time RESET is low should exceed 200 ms to make sure that the internal timer that controls the DS12887 on power-up has timed out.When RESET is low and Vcc is above 4.25 volts,the following occurs: 4of19
DS12887 4 of 19 occurs on the AS bus will clear the address regardless of whether CS is asserted. Access commands should be sent in pairs. DS (Data Strobe or Read Input) – The DS/RD pin has two modes of operation depending on the level of the MOT pin. When the MOT pin is connected to VCC, Motorola bus timing is selected. In this mode DS is a positive pulse during the latter portion of the bus cycle and is called Data Strobe. During read cycles, DS signifies the time that the DS12887 is to drive the bidirectional bus. In write cycles the trailing edge of DS causes the DS12887 to latch the written data. When the MOT pin is connected to GND, Intel bus timing is selected. In this mode the DS pin is called Read (RD ).RD identifies the time period when the DS12887 drives the bus with read data. The RD signal is the same definition as the Output Enable (OE ) signal on a typical memory. R/ W (Read/Write Input) – The R/ W pin also has two modes of operation. When the MOT pin is connected to VCC for Motorola timing, R/ W is at a level which indicates whether the current cycle is a read or write. A read cycle is indicated with a high level on R/ W while DS is high. A write cycle is indicated when R/ W is low during DS. When the MOT pin is connected to GND for Intel timing, the R/ W signal is an active low signal called WR. In this mode the R/ W pin has the same meaning as the Write Enable signal ( WE ) on generic RAMs. CS (Chip Select Input) – The Chip Select signal must be asserted low for a bus cycle in the DS12887 to be accessed. CS must be kept in the active state during DS and AS for Motorola timing and during RD and WR for Intel timing. Bus cycles which take place without asserting CS will latch addresses but no access will occur. When VCC is below 4.25 volts, the DS12887 internally inhibits access cycles by internally disabling the CS input. This action protects both the real time clock data and RAM data during power outages. IRQ (Interrupt Request Output) – The IRQ pin is an active low output of the DS12887 that can be used as an interrupt input to a processor. The IRQ output remains low as long as the status bit causing the interrupt is present and the corresponding interrupt–enable bit is set. To clear the IRQ pin the processor program normally reads the C register. The RESET pin also clears pending interrupts. When no interrupt conditions are present, the IRQ level is in the high impedance state. Multiple interrupting devices can be connected to an IRQ bus. The IRQ bus is an open drain output and requires an external pullup resistor. RESET (Reset Input) – The RESET pin has no effect on the clock, calendar, or RAM. On power–up the RESET pin can be held low for a time in order to allow the power supply to stabilize. The amount of time that RESET is held low is dependent on the application. However, if RESET is used on power–up, the time RESET is low should exceed 200 ms to make sure that the internal timer that controls the DS12887 on power-up has timed out. When RESET is low and VCC is above 4.25 volts, the following occurs:
DS12887 a Periodic Interrupt enable (pel)bit is cleared to o B.Alarm Interrupt Enable (AIE)bit is cleared to 0. C.Update Ended Interrupt Flag (UF)bit is cleared to 0. (IRQF)bit is cleared to F The device is not accessible until RESET is returned high G.Alarm Interrupt Flag(AF)bit is cleared to 0. H IRQ pin is in the high impedance state. L Square wave Output enable SOwe bit is cleared to o Update Ended Inte errupt Enable(UIE)is cleared to 0. In a typical application RESET can be connected to Vcc.This connection will allow the DS12887 to go in and out of power fail without affecting any of the control registers. s map the DS12887 is sho for control and status.All 128 bytes can be directly written or read except for the following: Registers C and D are read-only. 2.Bit 7 of Register A is read-only 3.The high order bit of the seconds byte is read-only The contents of four registers(A,B,C,and D)are described in the"Registers"section. ADDRESS MAP DS12887 Figure 2 SECONOS 14 MNUTES ALARM HOURS ALARM DAY OF THE WEEN DAY OF THE MONTH MONTH YEAR REG/STERA REGISTERB 5of19
DS12887 5 of 19 A. Periodic Interrupt Enable (PEI) bit is cleared to 0. B. Alarm Interrupt Enable (AIE) bit is cleared to 0. C. Update Ended Interrupt Flag (UF) bit is cleared to 0. D. Interrupt Request Status Flag (IRQF) bit is cleared to 0. E. Periodic Interrupt Flag (PF) bit is cleared to 0. F. The device is not accessible until RESET is returned high. G. Alarm Interrupt Flag (AF) bit is cleared to 0. H. IRQ pin is in the high impedance state. I. Square Wave Output Enable ( SQWE ) bit is cleared to 0. J. Update Ended Interrupt Enable (UIE) is cleared to 0. In a typical application RESET can be connected to VCC. This connection will allow the DS12887 to go in and out of power fail without affecting any of the control registers. ADDRESS MAP The address map of the DS12887 is shown in Figure 2. The address map consists of 114 bytes of user RAM, 10 bytes of RAM that contain the RTC time, calendar, and alarm data, and 4 bytes which are used for control and status. All 128 bytes can be directly written or read except for the following: 1. Registers C and D are read–only. 2. Bit 7 of Register A is read–only. 3. The high order bit of the seconds byte is read–only. The contents of four registers (A,B,C, and D) are described in the “Registers” section. ADDRESS MAP DS12887 Figure 2