Topic2:FPGA Design with Verilog FPGA Design Method Design flow tools Deign Model of Verilog HDL Design style of Verilog HDL Design Examples 。RTL level design Components of Datapath Components of Controller Supplementary 。Synthesizable ·Some experiences 。Other syntax rules 2021/1/13 ASIC Design,by Yan Bo 8
ASIC Design, by Yan Bo Topic2： FPGA Design with Verilog FPGA Design Method Design flow & tools Deign Model of Verilog HDL Design style of Verilog HDL Design Examples • RTL level design • Components of Datapath • Components of Controller Supplementary • Synthesizable • Some experiences • Other syntax rules 2021/1/13 8
Some experiences >Balance architecture Share resources Gated signal >Assignment statement Accident Intentional Latch 2021/1/13 ASIC Design,by Yan Bo 9
ASIC Design, by Yan Bo Some experiences 2021/1/13 9 ➢ Balance architecture ➢ Share resources ➢ Gated signal ➢Assignment statement ➢ Accident / Intentional Latch
Some experiences Balance architecture Share resources Gated signal >Assignment statement Accident Intentional Latch 2021/1/13 ASIC Design,by Yan Bo 10
ASIC Design, by Yan Bo Some experiences 2021/1/13 10 ➢ Balance architecture ➢ Share resources ➢ Gated signal ➢Assignment statement ➢ Accident / Intentional Latch
Balancing Operators a,b,c,d:4-bit vectors Unbalanced Balanced out a b c d out =(a b)*(c d) a 4X4 a 4X4 8X4 8X8 12x4 回 4X4 16-bit 16-bit Delay through 3 Stages of Multiply Delay through 2 Stages of Multiply 2021/1/13 ASIC Design,by Yan Bo 11
ASIC Design, by Yan Bo Balancing Operators a, b, c, d: 4-bit vectors out = a * b * c * d X a b X c X d z X a b out = (a * b) * (c * d) X c d X z Unbalanced Balanced 4 x 4 8 x 4 12 x 4 16-bit 4 x 4 4 x 4 8 x 8 16-bit Delay through 3 Stages of Multiply Delay through 2 Stages of Multiply 2021/1/13 11
Balancing Operators (Cont.) Data in register register register register h(o) h(1) h(2) h(3) Data out Use Parenthesis to Define Logic Groupings Increases Performance Utilization >Balances Delay from All Inputs to Output Circuit Functionality Unchanged 2021/1/13 ASIC Design,by Yan Bo 12
ASIC Design, by Yan Bo Balancing Operators （Cont.） 2021/1/13 12 Use Parenthesis to Define Logic Groupings ➢ Increases Performance & Utilization ➢ Balances Delay from All Inputs to Output ➢ Circuit Functionality Unchanged