方法一:布尔表达式 LBRARY EER USE IEEE STD LOG1C 1164.ALLY ENTITY ands PORT (a, b, C: IN STD_LOGIC; y OUT STD_LOGICE END and3- ARCHITECTURE and3 1 OF and3 s BEGIN y <=a AND b AND c) END and3_1
方法一：布尔表达式 LIBRARY IEEE; USE IEEE.STD_LOG1C_1164.ALL; ENTITY and3 IS PORT (a, b, c : IN STD_LOGIC; y : OUT STD_LOGIC); END and3; ARCHITECTURE and3_1 OF and3 IS BEGIN y <= (a AND b AND c) ; END and3_1;
方法二:逻辑真值描述 LBRARY=日 USE IEEE STD_LOGIC_-1164ALLi ENTITY and3 S PORT (a, b, C: IN STD_LOGIC; y OUT STD_LOGIC); END and35 ARCHTECTURE and32 OF ands BEGIN t4: PROCESS (a, b, c) VARIABLE comb:STD_LOGIC_VECTOR(2 DOWNTO O)B BEGIN combe=a &b
方法二：逻辑真值描述 LIBRARY IEEE; USE IEEE STD_LOGIC_1164.ALL; ENTITY and3 IS PORT (a，b，c : IN STD_LOGIC; y : OUT STD_LOGIC); END and3; ARCHITECTURE and3_2 OF and3 IS BEGIN t4: PROCESS (a，b，c) VARIABLE comb:STD_LOGIC_VECTOR(2 DOWNTO 0); BEGIN comb := a & b & c;
CASE comb s WHEN“000”〓 y≤=0 WEN“004=>y≤=07 wEN“o10s>y≤=0 MEN“01s>y≤=0 wEN“100=>y≤=0 MEN“101”s>y≤=0 WEN“110=>y<= WHEN“111”=>y<=1 WHEN OTHERS=>y≤=x END CASE END PROCESSE END and3_2
CASE comb IS WHEN “000” => y <=‘0’; WHEN “001” => y <=‘0’; WHEN “010” => y <=‘0’; WHEN “011” => y <=‘0’; WHEN “100” => y <=‘0’; WHEN “101” => y <=‘0’; WHEN “110” => y <=‘0’; WHEN “111” => y <=‘1’; WHEN OTHERS=> y <=‘X’; END CASE; END PROCESS; END and3_2;
编码译码器设计 三八译码器 优先级编码器
编码译码器设计 • 三八译码器 • 优先级编码器
优先级编码器 第一步:端口?实体设计…… input input1 yO input2 input y1 input4 inputs y2 inputs input
优先级编码器 • 第一步：端口？实体设计…… input0 input1 input2 input3 input4 input5 input6 input7 y0 y2 y1 74LS148