Tomasulo Example Cycle8WriteExecutionInstructionstatusTBusyInstructionIssuecompleteResultAddressR2LDF634+34Load1No124LDR35F245+Load2No3F2F4NoMULTIFOLoad3F6F2478SUBDF85FOF6DIVDF10F8F26ADDDF6S1S2RSforjRSforkReservationStationsViVkQjQkTime NameBusyOpNo0Add12 Add2M(45+R3)YesADDD M()-MONo0 Add3R(F4)7 Mult1YesMULTDM(45+R3)Mult10Mult2YesDIVDM(34+R2)RegisterresultstatusF2F4FOF6F8F10ClockF12F308FUAdd2Mult1M(45+R3)MO-MOMult2ComputerArchitecture
Computer Architecture Tomasulo Example Cycle 8 Instruction status Execution Write Instruction j k Issue complete Result Busy Address LD F6 34+ R2 1 3 4 Load1 No LD F2 45+ R3 2 4 5 Load2 No MULTDF0 F2 F4 3 Load3 No SUBD F8 F6 F2 4 7 8 DIVD F10 F0 F6 5 ADDD F6 F8 F2 6 Reservation Stations S1 S2 RS for j RS for k Time Name Busy Op Vj Vk Qj Qk 0 Add1 No 2 Add2 Yes ADDD M()-M() M(45+R3) 0 Add3 No 7 Mult1 Yes MULTD M(45+R3) R(F4) 0 Mult2 Yes DIVD M(34+R2) Mult1 Register result status Clock F0 F2 F4 F6 F8 F10 F12 . F30 8 FU Mult1 M(45+R3) Add2 M()-M() Mult2
Tomasulo Example Cycle9ExecutionWriteInstructionstatuskIssueResultBusyInstructioncompleteAddressR2LD34+3NoF614Load1245LDF245+R3Load2NoF43MULTIFOF2NoLoad3F2478F6SUBDF85FOF6DIVDF106F8F2ADDDF6S1S2RSforjRSforkReservationStationsViVkQjQkTimeBusyOpName0 Add1No1Add2YesADDDMO-MOM(45+R3)0Add3No6 Mult1YesMULTDM(45+R3)R(F4)0Mult2DIVDMult1YesM(34+R2)RegisterresultstatusF4FOF2F6F8F30ClockF10F129FUMult1Add2M(45+R3)MO-MOMult2ComputerArchitecture
Computer Architecture Tomasulo Example Cycle 9 Instruction status Execution Write Instruction j k Issue complete Result Busy Address LD F6 34+ R2 1 3 4 Load1 No LD F2 45+ R3 2 4 5 Load2 No MULTDF0 F2 F4 3 Load3 No SUBD F8 F6 F2 4 7 8 DIVD F10 F0 F6 5 ADDD F6 F8 F2 6 Reservation Stations S1 S2 RS for j RS for k Time Name Busy Op Vj Vk Qj Qk 0 Add1 No 1 Add2 Yes ADDD M()–M() M(45+R3) 0 Add3 No 6 Mult1 Yes MULTD M(45+R3) R(F4) 0 Mult2 Yes DIVD M(34+R2) Mult1 Register result status Clock F0 F2 F4 F6 F8 F10 F12 . F30 9 FU Mult1 M(45+R3) Add2 M()–M() Mult2
Tomasulo Example Cycle 10ExecutionWriteInstructionstatuskIssueResultBusyInstructioncompleteAddressR2LD34+3NoF614Load1245LDF245+R3Load2NoF43MULTIFOF2NoLoad3F2478F6SUBDF8FOF65DIVDF106F8F210ADDDF6S2S1RSforjRSforkReservationStationsViVkQjQkBusyOpTimeName0 Add1No0Add2YesADDDMO-MOM(45+R3)0Add3No5 Mult1YesMULTDM(45+R3)R(F4)0Mult2DIVDMult1YesM(34+R2)RegisterresultstatusF4FOF2F6F8F30ClockF10F1210FUMult1Add2M(45+R3)MO-MOMult2ComputerArchitecture
Computer Architecture Instruction status Execution Write Instruction j k Issue complete Result Busy Address LD F6 34+ R2 1 3 4 Load1 No LD F2 45+ R3 2 4 5 Load2 No MULTDF0 F2 F4 3 Load3 No SUBD F8 F6 F2 4 7 8 DIVD F10 F0 F6 5 ADDD F6 F8 F2 6 10 Reservation Stations S1 S2 RS for j RS for k Time Name Busy Op Vj Vk Qj Qk 0 Add1 No 0 Add2 Yes ADDD M()–M() M(45+R3) 0 Add3 No 5 Mult1 Yes MULTD M(45+R3) R(F4) 0 Mult2 Yes DIVD M(34+R2) Mult1 Register result status Clock F0 F2 F4 F6 F8 F10 F12 . F30 10 FU Mult1 M(45+R3) Add2 M()–M() Mult2 Tomasulo Example Cycle 10
Tomasulo Example Cycle 11ExecutionWriteInstruction statuskResultBusyAddressInstructionIssuecompleteLDF634+R2134Load1No425R3LDF245+Load2No3F2F4MULTIFOLoad3NoF2478F6SUBDF85FODIVDF10F6F8F261011ADDDF6S1S2RSforjRSforkReservationStationsViVkQjQkBusyOpTime NameNo0 Add10 Add2NoNo0 Add34Mult1MULTDM(45+R3)R(F4)YesDIVDMult10Mult2YesM(34+R2)RegisterresultstatusFoF2F4F6F8ClockF10F12F3011FUMult1M(45+R3)(M-M)+MOMult2MO-MOComputerArchitecture
Computer Architecture Tomasulo Example Cycle 11 Instruction status Execution Write Instruction j k Issue complete Result Busy Address LD F6 34+ R2 1 3 4 Load1 No LD F2 45+ R3 2 4 5 Load2 No MULTDF0 F2 F4 3 Load3 No SUBD F8 F6 F2 4 7 8 DIVD F10 F0 F6 5 ADDD F6 F8 F2 6 10 11 Reservation Stations S1 S2 RS for j RS for k Time Name Busy Op Vj Vk Qj Qk 0 Add1 No 0 Add2 No 0 Add3 No 4 Mult1 Yes MULTD M(45+R3) R(F4) 0 Mult2 Yes DIVD M(34+R2) Mult1 Register result status Clock F0 F2 F4 F6 F8 F10 F12 . F30 11 FU Mult1 M(45+R3) (M-M)+M() M()–M() Mult2
Tomasulo Example Cycle 12ExecutionWriteInstructionstatuskResultInstructionIssueBusyAddresscompleteLDF634+R2341Load1No2LDF2R34545+Load2No3F2F4MULTIFOLoad3No7F6F248SUBDF85FOF6DIVDF101011F8F26ADDDF6S1S2RSforjRSforkReservationStationsVjVkBusy OpQjQkTimeNameNo0 Add10 Add2No0 Add3NoR(F4)3 Mult1YesMULTDM(45+R3)o Mult2DIVDM(34+R2)Mult1YesRegisterresultstatusF4FOF2F6F8ClockF10F30F1212FUMult1M(45+R3)Mult2(M-M)+MOMO-MOComputerArchitecture
Computer Architecture Tomasulo Example Cycle 12 Instruction status Execution Write Instruction j k Issue complete Result Busy Address LD F6 34+ R2 1 3 4 Load1 No LD F2 45+ R3 2 4 5 Load2 No MULTDF0 F2 F4 3 Load3 No SUBD F8 F6 F2 4 7 8 DIVD F10 F0 F6 5 ADDD F6 F8 F2 6 10 11 Reservation Stations S1 S2 RS for j RS for k Time Name Busy Op Vj Vk Qj Qk 0 Add1 No 0 Add2 No 0 Add3 No 3 Mult1 Yes MULTD M(45+R3) R(F4) 0 Mult2 Yes DIVD M(34+R2) Mult1 Register result status Clock F0 F2 F4 F6 F8 F10 F12 . F30 12 FU Mult1 M(45+R3) (M-M)+M() M()–M() Mult2