Tomasulo Example Cycle 13ExecutionWriteInstructionstatuskIssueResultBusyInstructioncompleteAddressR2LD34+3NoF614Load1245LDF245+R3Load2NoF43MULTIFOF2NoLoad3F2478F6SUBDF8FOF65DIVDF10611F8F210ADDDF6S1S2RSforjRSforkReservationStationsviVkQjQkBusyOpTimeName0 Add1NoNo0Add2Add3No2 Mult1YesMULTDM(45+R3)R(F4)0 Mult2DIVDMult1YesM(34+R2)RegisterresultstatusF4FOF2F6F8F30ClockF10F1213FUMult1M(45+R3)(M-M)+MOMO-MOMult2ComputerArchitecture
Computer Architecture Tomasulo Example Cycle 13 Instruction status Execution Write Instruction j k Issue complete Result Busy Address LD F6 34+ R2 1 3 4 Load1 No LD F2 45+ R3 2 4 5 Load2 No MULTDF0 F2 F4 3 Load3 No SUBD F8 F6 F2 4 7 8 DIVD F10 F0 F6 5 ADDD F6 F8 F2 6 10 11 Reservation Stations S1 S2 RS for j RS for k Time Name Busy Op Vj Vk Qj Qk 0 Add1 No 0 Add2 No Add3 No 2 Mult1 Yes MULTD M(45+R3) R(F4) 0 Mult2 Yes DIVD M(34+R2) Mult1 Register result status Clock F0 F2 F4 F6 F8 F10 F12 . F30 13 FU Mult1 M(45+R3) (M–M)+M() M()–M() Mult2
Tomasulo Example Cycle 14ExecutionWriteInstructionstatuskIssueResultBusyInstructioncompleteAddressR2LD34+3F614Load1No245LDF245+R3Load2No3MULTIFOF2F4NoLoad3F2478F6SUBDF8FOF65DIVDF10611F8F210ADDDF6S1S2RSforjRSforkReservationStationsviVkQjQkBusyOpTimeName0 Add1NoNo0Add2No0Add31Mult1YesMULTDM(45+R3)R(F4)0Mult2DIVDMult1YesM(34+R2)RegisterresultstatusF4FOF2F6F8F30ClockF10F1214FUMult1M(45+R3)(M-M)+MOMO-MOMult2ComputerArchitecture
Computer Architecture Tomasulo Example Cycle 14 Instruction status Execution Write Instruction j k Issue complete Result Busy Address LD F6 34+ R2 1 3 4 Load1 No LD F2 45+ R3 2 4 5 Load2 No MULTDF0 F2 F4 3 Load3 No SUBD F8 F6 F2 4 7 8 DIVD F10 F0 F6 5 ADDD F6 F8 F2 6 10 11 Reservation Stations S1 S2 RS for j RS for k Time Name Busy Op Vj Vk Qj Qk 0 Add1 No 0 Add2 No 0 Add3 No 1 Mult1 Yes MULTD M(45+R3) R(F4) 0 Mult2 Yes DIVD M(34+R2) Mult1 Register result status Clock F0 F2 F4 F6 F8 F10 F12 . F30 14 FU Mult1 M(45+R3) (M–M)+M() M()–M() Mult2
Tomasulo Example Cycle 15ExecutionWriteInstruction statuskResultIssuecompleteBusyAddressInstructionR2344NoLDF634+1Load125LDF245+R3Load2NoF43F215Load3NoMULTIFO78F6F24SUBDF85FOF6DIVD F10F2F861011ADDDF6S1S2RSforjRSforkReservationStationsVjVkQjQkTime NameBusyOp0 Add1NoNo0 Add2Add3No0 Mult1YesMULTDM(45+R3)R(F4)0 Mult2DIVDM(34+R2)Mult1YesRegisterresultstatusF4FOF2F6F8F10F12F30Clock15FUMult1M(45+R3)(M-M)+MOMO-MOMult2ComputerArchitecture
Computer Architecture Tomasulo Example Cycle 15 Instruction status Execution Write Instruction j k Issue complete Result Busy Address LD F6 34+ R2 1 3 4 Load1 No LD F2 45+ R3 2 4 5 Load2 No MULTDF0 F2 F4 3 15 Load3 No SUBD F8 F6 F2 4 7 8 DIVD F10 F0 F6 5 ADDD F6 F8 F2 6 10 11 Reservation Stations S1 S2 RS for j RS for k Time Name Busy Op Vj Vk Qj Qk 0 Add1 No 0 Add2 No Add3 No 0 Mult1 Yes MULTD M(45+R3) R(F4) 0 Mult2 Yes DIVD M(34+R2) Mult1 Register result status Clock F0 F2 F4 F6 F8 F10 F12 . F30 15 FU Mult1 M(45+R3) (M–M)+M() M()–M() Mult2
Tomasulo Example Cycle 16ExecutionWriteInstruction statuskResultIssuecompleteBusyAddressInstructionR234NoLDF634+14Load125LDF245+R3Load2NoF4316F215Load3NoMULTIFO7F28F64SUBDF85FOF6DIVD F10F2F861011ADDDF6S1S2RSforjRSforkReservationStationsVjVkQjQkTime NameBusyOp0 Add1NoNo0 Add2Add3NoNo0 Mult1DIVDM*F4M(34+R2)40Mult2YesRegisterresultstatusF4FOF2F6F8F10F12F30Clock16FUM*F4M(45+R3)(M-M)+MOMO-MOMult2ComputerArchitecture
Computer Architecture Tomasulo Example Cycle 16 Instruction status Execution Write Instruction j k Issue complete Result Busy Address LD F6 34+ R2 1 3 4 Load1 No LD F2 45+ R3 2 4 5 Load2 No MULTDF0 F2 F4 3 15 16 Load3 No SUBD F8 F6 F2 4 7 8 DIVD F10 F0 F6 5 ADDD F6 F8 F2 6 10 11 Reservation Stations S1 S2 RS for j RS for k Time Name Busy Op Vj Vk Qj Qk 0 Add1 No 0 Add2 No Add3 No 0 Mult1 No 40 Mult2 Yes DIVD M*F4 M(34+R2) Register result status Clock F0 F2 F4 F6 F8 F10 F12 . F30 16 FU M*F4 M(45+R3) (M–M)+M() M()–M() Mult2
TomasuloExampleCycle55ExecutionWriteInstruction statuskResultIssuecompleteBusyAddressInstructionR234NoLDF634+14Load125LDF245+R3Load2NoF4316F215Load3NoMULTIFO7F28F64SUBDF85FOF6DIVD F10F2F861011ADDDF6S1S2RSforjRSforkReservationStationsVjVkQjQkTime NameBusyOp0 Add1NoNo0 Add2Add3NoNo0 Mult11 Mult2DIVDM*F4M(34+R2)YesRegisterresultstatusF4FOF2F6F8F10F12F30Clock55FUM*F4M(45+R3)(M-M)+MOMO-MOMult2ComputerArchitecture
Computer Architecture Tomasulo Example Cycle 55 Instruction status Execution Write Instruction j k Issue complete Result Busy Address LD F6 34+ R2 1 3 4 Load1 No LD F2 45+ R3 2 4 5 Load2 No MULTDF0 F2 F4 3 15 16 Load3 No SUBD F8 F6 F2 4 7 8 DIVD F10 F0 F6 5 ADDD F6 F8 F2 6 10 11 Reservation Stations S1 S2 RS for j RS for k Time Name Busy Op Vj Vk Qj Qk 0 Add1 No 0 Add2 No Add3 No 0 Mult1 No 1 Mult2 Yes DIVD M*F4 M(34+R2) Register result status Clock F0 F2 F4 F6 F8 F10 F12 . F30 55 FU M*F4 M(45+R3) (M–M)+M() M()–M() Mult2