Tomasulo Example Cycle 3ExecutionWriteInstructionstatuskIssueResultBusyInstructioncompleteAddressLD34+R2Load1F613Yes34+R2F2R32LD45+Load2Yes45+R3F2F43NoMULTIFOLoad3F2F6SUBDF8FOF6DIVDF10F8F2ADDDF6S1S2RSforjRSforkReservationStationsVVkQjQkTimeNameBusyOp0Add1NoNo0 Add2Add3NoMULTDLoad20Mult1YesR(F4)0 Mult2NoRegisterresultstatusFOF2F4F6F8F10F30ClockF123FUMult1Load1Load2ComputerArchitecture
Computer Architecture Tomasulo Example Cycle 3 Instruction status Execution Write Instruction j k Issue complete Result Busy Address LD F6 34+ R2 1 3 Load1 Yes 34+R2 LD F2 45+ R3 2 Load2 Yes 45+R3 MULTDF0 F2 F4 3 Load3 No SUBD F8 F6 F2 DIVD F10 F0 F6 ADDD F6 F8 F2 Reservation Stations S1 S2 RS for j RS for k Time Name Busy Op Vj Vk Qj Qk 0 Add1 No 0 Add2 No Add3 No 0 Mult1 Yes MULTD R(F4) Load2 0 Mult2 No Register result status Clock F0 F2 F4 F6 F8 F10 F12 . F30 3 FU Mult1 Load2 Load1
Tomasulo Example Cycle 4WriteInstructionstatusExecutionkIssueResultBusyAddressInstructioncompleteR2LDF634+34Load1No12LDR3445+R3F245+Load2Yes3F2F4MULTIFOLoad3NoF24F6SUBDF8F6DIVD F10FOF2F8ADDDF6S1S2RSforjRSforkReservationStationsviVkQjQkTime NameBusyOp0 Add1YesSUBDM(34+R2)Load20 Add2NoAdd3NoR(F4)Load20Mult1YesMULTD0 Mult2NoRegisterresultstatusFOF2F4F6F8ClockF10F12F304FUMult1Load2M(34+R2)Add1ComputerArchitecture
Computer Architecture Tomasulo Example Cycle 4 Instruction status Execution Write Instruction j k Issue complete Result Busy Address LD F6 34+ R2 1 3 4 Load1 No LD F2 45+ R3 2 4 Load2 Yes 45+R3 MULTDF0 F2 F4 3 Load3 No SUBD F8 F6 F2 4 DIVD F10 F0 F6 ADDD F6 F8 F2 Reservation Stations S1 S2 RS for j RS for k Time Name Busy Op Vj Vk Qj Qk 0 Add1 Yes SUBD M(34+R2) Load2 0 Add2 No Add3 No 0 Mult1 Yes MULTD R(F4) Load2 0 Mult2 No Register result status Clock F0 F2 F4 F6 F8 F10 F12 . F30 4 FU Mult1 Load2 M(34+R2) Add1
Tomasulo Example Cycle5ExecutionWriteInstructionstatuskjIssueResultBusyInstructioncompleteAddressR234LDF634+14Load1No25R3NoLDF245+Load2F43MULTIFOF2Load3NoF6F24SUBDF85F6FODIVDF10F8F2ADDDF6S1S2RSforjRSforkReservationStationsVjVkQjQkTimeNameBusyOp2 Add1YesSUBDM(34+R2)M(45+R3)0 Add2NoAdd3No10Mult1MULTD M(45+R3)R(F4)YesMult10 Mult2YesDIVDM(34+R2)RegisterresultstatusF4FoF2F6F8F10F12F30Clock5FUMult1M(45+R3)M(34+R2)Add1Mult2ComputerArchitecture
Computer Architecture Tomasulo Example Cycle 5 Instruction status Execution Write Instruction j k Issue complete Result Busy Address LD F6 34+ R2 1 3 4 Load1 No LD F2 45+ R3 2 4 5 Load2 No MULTDF0 F2 F4 3 Load3 No SUBD F8 F6 F2 4 DIVD F10 F0 F6 5 ADDD F6 F8 F2 Reservation Stations S1 S2 RS for j RS for k Time Name Busy Op Vj Vk Qj Qk 2 Add1 Yes SUBD M(34+R2) M(45+R3) 0 Add2 No Add3 No 10 Mult1 Yes MULTD M(45+R3) R(F4) 0 Mult2 Yes DIVD M(34+R2) Mult1 Register result status Clock F0 F2 F4 F6 F8 F10 F12 . F30 5 FU Mult1 M(45+R3) M(34+R2) Add1 Mult2
Tomasulo Example Cycle 6WriteExecutionInstructionstatuskIssueResultBusyAddressInstructioncompleteLDR234Load1NoF634+124LDF2R3545+Load2No3F4MULTIFOF2NoLoad3F2F64SUBDF8F65DIVDF10FOF26F8ADDDF6S1S2RSforjReservationStationsRSforkviVkQjQkTimeNameBusyOp1 Add1YesSUBDM(34+R2)M(45+R3)0 Add2YesAdd1ADDDM(45+R3)Add3NoR(F4)9Mult1YesMULTDM(45+R3)0 Mult2YesDIVDM(34+R2)Mult1RegisterresultstatusFOF2F6F4F8F10F12F30Clock6FUMult1M(45+R3)Add2Add1Mult2ComputerArchitecture
Computer Architecture Tomasulo Example Cycle 6 Instruction status Execution Write Instruction j k Issue complete Result Busy Address LD F6 34+ R2 1 3 4 Load1 No LD F2 45+ R3 2 4 5 Load2 No MULTDF0 F2 F4 3 Load3 No SUBD F8 F6 F2 4 DIVD F10 F0 F6 5 ADDD F6 F8 F2 6 Reservation Stations S1 S2 RS for j RS for k Time Name Busy Op Vj Vk Qj Qk 1 Add1 Yes SUBD M(34+R2) M(45+R3) 0 Add2 Yes ADDD M(45+R3) Add1 Add3 No 9 Mult1 Yes MULTD M(45+R3) R(F4) 0 Mult2 Yes DIVD M(34+R2) Mult1 Register result status Clock F0 F2 F4 F6 F8 F10 F12 . F30 6 FU Mult1 M(45+R3) Add2 Add1 Mult2
Tomasulo Example Cycle 7ExecutionWriteInstructionstatuskIssueResultBusyAddressInstructioncompleteLDF634+R2Load1No134245LDF2R345+Load2NoF2F43NoMULTIFOLoad37F6F24SUBDF8FOF65DIVD F106F2F8ADDDF6S1S2RSforjRSforkReservationStationsviVkQjQkTimeNameBusyOp0Add1YesSUBDM(34+R2)M(45+R3)Add10 Add2YesADDDM(45+R3)NoAdd3YesR(F4)8Mult1MULTDM(45+R3）Mult10 Mult2YesDIVDM(34+R2)RegisterresultstatusFoF2F4F6F8F10F12F30Clock7FUMult1Add2Add1Mult2M(45+R3)ComputerArchitecture
Computer Architecture Tomasulo Example Cycle 7 Instruction status Execution Write Instruction j k Issue complete Result Busy Address LD F6 34+ R2 1 3 4 Load1 No LD F2 45+ R3 2 4 5 Load2 No MULTDF0 F2 F4 3 Load3 No SUBD F8 F6 F2 4 7 DIVD F10 F0 F6 5 ADDD F6 F8 F2 6 Reservation Stations S1 S2 RS for j RS for k Time Name Busy Op Vj Vk Qj Qk 0 Add1 Yes SUBD M(34+R2) M(45+R3) 0 Add2 Yes ADDD M(45+R3) Add1 Add3 No 8 Mult1 Yes MULTD M(45+R3) R(F4) 0 Mult2 Yes DIVD M(34+R2) Mult1 Register result status Clock F0 F2 F4 F6 F8 F10 F12 . F30 7 FU Mult1 M(45+R3) Add2 Add1 Mult2