WritebackandCommonDataBusNormal data bus: data + destination ("go to"bus)Common data bus: data + source ("come from" bus)- 64 bits of data+4bits of source index (tag)-DoesthebroadcasttoeveryinstructionintheflyChild instructions do tag matching and update their ready bitsandvaluefields(ifthetagmatchestheirs)ComputerArchitecture
Computer Architecture Writeback and Common Data Bus • Normal data bus: data + des?na?on (“go to” bus) • Common data bus: data + source (“come from” bus) – 64 bits of data + 4 bits of source index (tag) – Does the broadcast to every instruc?on in the fly • Child instruc?ons do tag matching and update their ready bits and value fields (if the tag matches theirs)
CodeExampleLDF6,34(R2)LD1LD2LDF2,45(R3)MULTIFO,F2,F4MULTISUBDSUBDF8,F6,F2DIVDF10,F0,F6ADDF6,F8,F2DIVDADDOperationlatencies:load/store2cyclesAdd/sub 2 cycles, Mult 10 cycles, divide 40 cycleComputerArchitecture
Computer Architecture Code Example LD F6,34(R2) LD F2,45(R3) MULTI F0,F2,F4 SUBD F8,F6,F2 DIVD F10,F0,F6 ADD F6,F8,F2 LD1 LD2 SUBD MULTI ADD DIVD Opera3on latencies: load/store 2 cycles, Add/sub 2 cycles, Mult 10 cycles, divide 40 cycle
Tomasulo Example Cycle 0WriteInstructionstatusExecutionkResultBusyInstructionIssuecompleteAddressR234+NoLDF6Load1LDR3F245+Load2NoF2F4MULTIFONoLoad3F6F2SUBDF8F6DIVD F10FOF8F2ADDDF6S1S2RS forjRSforkReservationStationsViVkQQkTimeNameBusyOpNo0 Add10 Add2No0Add3NoNo0Mult10 Mult2NoRegisterresultstatusF2F4F8FOF6F10F12F30Clock0FUComputerArchitecture
Computer Architecture Tomasulo Example Cycle 0 Instruction status Execution Write Instruction j k Issue complete Result Busy Address LD F6 34+ R2 Load1 No LD F2 45+ R3 Load2 No MULTDF0 F2 F4 Load3 No SUBD F8 F6 F2 DIVD F10 F0 F6 ADDD F6 F8 F2 Reservation Stations S1 S2 RS for j RS for k Time Name Busy Op Vj Vk Qj Qk 0 Add1 No 0 Add2 No 0 Add3 No 0 Mult1 No 0 Mult2 No Register result status Clock F0 F2 F4 F6 F8 F10 F12 . F30 0 FU
Tomasulo Example Cycle 1InstructionstatusExecutionWritekIssueResultBusyAddressInstructioncompleteR234+LDF61Load1Yes34+R2LDR3F245+Load2NoF2F4MULTIFONoLoad3F6F2SUBDF8F6DIVD F10FOF8F2ADDDF6S1S2RS forjRSforkReservation StationsViVkQQkTimeNameBusyOpNo0 Add10 Add2NoAdd3NoNo0Mult10 Mult2NoRegisterresultstatusF2F4F8ClockFOF6F10F12F301FULoad1ComputerArchitecture
Computer Architecture Tomasulo Example Cycle 1 Instruction status Execution Write Instruction j k Issue complete Result Busy Address LD F6 34+ R2 1 Load1 Yes 34+R2 LD F2 45+ R3 Load2 No MULTDF0 F2 F4 Load3 No SUBD F8 F6 F2 DIVD F10 F0 F6 ADDD F6 F8 F2 Reservation Stations S1 S2 RS for j RS for k Time Name Busy Op Vj Vk Qj Qk 0 Add1 No 0 Add2 No Add3 No 0 Mult1 No 0 Mult2 No Register result status Clock F0 F2 F4 F6 F8 F10 F12 . F30 1 FU Load1
Tomasulo Example Cycle 2ExecutionWriteInstructionstatusk丁IssueResultBusyAddressInstructioncompleteR2LDF634+1Load1Yes34+R22R3LDF245+Load2Yes45+R3F4MULTIFOF2Load3NoF6F2SUBDF8F6FODIVDF10F8F2ADDDF6S1S2RSforjRSforkReservationStationsVjVkQkQjTimeNameBusyOpNo0 Add1No0 Add2Add3NoNo0Mult10 Mult2NoRegisterresultstatusF2F4F8FF6F10F12F30Clock2FULoad2Load1ComputerArchitecture
Computer Architecture Tomasulo Example Cycle 2 Instruction status Execution Write Instruction j k Issue complete Result Busy Address LD F6 34+ R2 1 Load1 Yes 34+R2 LD F2 45+ R3 2 Load2 Yes 45+R3 MULTDF0 F2 F4 Load3 No SUBD F8 F6 F2 DIVD F10 F0 F6 ADDD F6 F8 F2 Reservation Stations S1 S2 RS for j RS for k Time Name Busy Op Vj Vk Qj Qk 0 Add1 No 0 Add2 No Add3 No 0 Mult1 No 0 Mult2 No Register result status Clock F0 F2 F4 F6 F8 F10 F12 . F30 2 FU Load2 Load1