ThreeStagesof Tomasulo Algorithm1. Issue-get instruction from FP Op QueueIf reservationstationfree (no structural hazard)issues instr & sends operands (renames registers)2. Execution-operate on operands (Ex)Whenbothoperandsreadythenexecute;if not ready,watch Common Data Bus for result3. Write result-finish execution (WB)Write on Common Data Bus to all awaiting units;markreservationstationavailableIssue:builddependencefornewinstWriteback:Wakeupdependent instructionsComputerArchitecture
Computer Architecture Three Stages of Tomasulo Algorithm 1. Issue—get instruc?on from FP Op Queue If reserva?on sta?on free (no structural hazard), issues instr & sends operands (renames registers). 2. Execution—operate on operands (EX) When both operands ready then execute; if not ready, watch Common Data Bus for result 3. Write result—finish execu?on (WB) Write on Common Data Bus to all awai?ng units; mark reserva?on sta?on available Issue: build dependence for new inst Writeback: Wakeup dependent instruc?ons
ILP: Tomasulo Algorithm - An ExampleExplanationsofeachstages,AbigexampleComputerArchitecture
Computer Architecture ILP: Tomasulo Algorithm – An Example Explana?ons of each stages, A big example
ThreeStagesofTomasuloAlgorithm1.Issue-get instructionfromFPOpQueueIf reservation stationfree (no structural hazard)issues instr & sends operands (renames registers).2. Execution-operate on operands (Ex)Whenbothoperands readythenexecute;if not ready, watch Common Data Bus for result3. Write result-finish execution (WB)Write on Common Data Bus to all awaiting units;markreservationstationavailableIssue:builddependencefornewinstWriteback:WakeupdependentinstructionsComputerArchitecture
Computer Architecture Three Stages of Tomasulo Algorithm 1. Issue—get instruc?on from FP Op Queue If reserva?on sta?on free (no structural hazard), issues instr & sends operands (renames registers). 2. Execution—operate on operands (EX) When both operands ready then execute; if not ready, watch Common Data Bus for result 3. Write result—finish execu?on (WB) Write on Common Data Bus to all awai?ng units; mark reserva?on sta?on available Issue: build dependence for new inst Writeback: Wakeup dependent instruc?ons
IssueStageandRenamingTableRenames its two sourceregisters (source renaming)AssignsittoafreeRsUpdates Renaming table (dest renaming). Also decodes the inst and read register values in parallelComputerArchitecture
Computer Architecture Issue Stage and Renaming Table • Renames its two source registers (source renaming) • Assigns it to a free RS • Updates Renaming table (dest renaming) • Also decodes the inst and read register values in parallel
ExecuteStage· Only"ready"instructions can join the competition: There is a select logic to select instructions for FUexecution- Some policy may be used, e.g. age basedNon-ready instructions can be“waken up" duringwriteback of its parent instComputerArchitecture
Computer Architecture Execute Stage • Only “ready” instruc?ons can join the compe??on • There is a select logic to select instruc?ons for FU execu?on – Some policy may be used, e.g. age based • Non-ready instruc?ons can be “waken up” during writeback of its parent inst