R FIGURE 24.17 Source followe Another circuit in which the dynamic drain-to-source resistance ra is important is the constant-current ource or current regulator diode. In this case the current regulation is directly proportional to the dynamic drain-to-source resistand Source follower Source. Follower Voltage Gain le will now consider the CD JFET configuration, which is also known as the source follower. A basic CD circuit is shown in Fig. 24.17. The input signal is supplied to the gate of the JFET. The output is taken from the source of the JFET, and the drain is connected directly to the Vpp supply voltage, which is ac gi vs and vs=is, Ret, where Rnet=[R sR,l is the net lar a vGs. For this CD circuit we also have that ves=VG For the JFET in the active region we have that d resistance driven by the transistor. Since vas =ias/gms we have that ias/gm= vG-ids Rnet. Collecting terms in ids on the left side yields ias[(1/gm)+Rne =vG,so (1/gn)+R The output voltage is YA =ve=iR=8m +8mr and thus the ac small-signal voltage gain is R Upon dividing through by gm this can be rewritten (1/gm)+R From this we see that the voltage gain will be positive, and thus the source follower is a noninverting amplifier We also note that Ay will always be less than unity, although for the usual case of Rnet >> 1/gm, the voltage gain will be close to unity. The source follower can be represented as an amplifier with an open-circuit (i. e, no load) voltage transfer ratio of unity and an output resistance of To=1/gm. The equation for Ay can be expressed as Ay= Re /(ret+ ro), which is the voltage division ratio of the ro=Ret circuit. c 2000 by CRC Press LLC
© 2000 by CRC Press LLC Another circuit in which the dynamic drain-to-source resistance rds is important is the constant-current source or current regulator diode. In this case the current regulation is directly proportional to the dynamic drain-to-source resistance. Source Follower Source-Follower Voltage Gain We will now consider the CD JFET configuration, which is also known as the source follower. A basic CD circuit is shown in Fig. 24.17. The input signal is supplied to the gate of the JFET. The output is taken from the source of the JFET, and the drain is connected directly to the VDD supply voltage, which is ac ground. For the JFET in the active region we have that ids = gmvGS . For this CD circuit we also have that vGS = vG – vS and vS = ids Rnet , where Rnet = [RS **RL] is the net load resistance driven by the transistor. Since vGS = ids/gm, we have that ids/gm = vG – ids Rnet. Collecting terms in ids on the left side yields ids[(1/gm) + Rnet] = vG , so The output voltage is and thus the ac small-signal voltage gain is Upon dividing through by gm this can be rewritten as From this we see that the voltage gain will be positive, and thus the source follower is a noninverting amplifier. We also note that AV will always be less than unity, although for the usual case of Rnet >> 1/gm, the voltage gain will be close to unity. The source follower can be represented as an amplifier with an open-circuit (i.e., no load) voltage transfer ratio of unity and an output resistance of rO = 1/gm . The equation for AV can be expressed as AV = Rnet /(Rnet + rO), which is the voltage division ratio of the rO = Rnet circuit. FIGURE 24.17 Source follower. i v g R g v g R ds G m m G m = + = (1 1 / ) net + net v v i R g R v g R O S ds m G m = = = + net net net 1 A v v g R g R V O G m m = = + net net 1 A R g R V m = + net net (1/ )
Source-Follower Examples Let's consider an example of a JFET with Ipss =10 mA and Vp=-4 V Let VDp =+20V and 5 mA. For Ips= Ipss/2 the value of Va is-1.17 V. To bias the JFET in the middle of the active region, we will let VGo= Vop/2=+10 V, VGQ-VGs =+10 V-(1.17 V)=+1117V. Thus Rs= Vso/ 11.17V/5mA=223k9. The transfer conductance at Ips =5 mA is 3. 54 mS so that ro=1/8m=283 Q2. Since 8m Rs =7.9, good bias tability will be obtained. If R,>>Rs, then Av= Rs/(ro rs)=2. 23 kQ/(283Q2+ 2.23 kQ2)=0.887. If I kQ, then Rnet=690 Q2, and Ay drops to 0.709, and if R,= 300 Q2, Rnet=264 Q2 and Ay is down to 0.483.A BJT emitter-follower circuit has the same equations for the voltage gain as the FET source follower. For the BJT case, ro=1/gm=VrlIo where Vr thermal voltage= kT/q= 25 mV and Ic is the quiescent collector current For Ic= 5 mA, we get To 25 mV/5 mA=5 Q2 as compared to ro =283 Q2 for the JFET case at the same quiescent current level. So the emitter follower does have a major advantage over the source follower since it has a much lower output resistance To and can thus drive very small load resistances with a voltage gain lose to unity. For example, with R,= 100 Q2, we get Ay=0. 26 for the source follower as compared to Ay= 0.95 for the emitter follower The FET source follower does, however, offer substantial advantages over the emitter follower of a much higher input resistance and a much lower input current. For the case in which a very high-impedance source, up in the megohm range, is to be coupled to a low-impedance load down in the range of 100 Q2 or less, a good combination to consider is that of a cascaded FET source follower followed by a B]T emitter follower. This combination offers the very high input resistance of the source follower and the very low output resistance of the emitter follower For the source-follower circuit under consideration the input resistance will be Rin=[RGI Rg)=10 MQ.If the jFet gate current is specified as 1 nA(max), and for good bias stability the change in gate voltage due to the gate current should not exceed v/10=0.4 V, the maximum allowable value for [Rgrg] is given by IG [RGI]<0.4V. Thus [RGI Ra]<0.4V/l nA=0.4 GQ2=400 MQ2. Therefore RGI and Ra can each be allowed to be as large as 800 MQ2, and very large values for Rin can thus be obtained. At higher frequencies the input capacitance Cn must be considered, and Cin will ultimately limit the input impedance of the circuit. Since the input capacitance of the Fet will be comparable to that of the B]T, the advantage of the FET source follower over the BjT emitter follower from the standpoint of input impedance will be obtained only at relatively low frequencies. Source-Follower Frequency Response The input capacitance of the source follower is given by Cn= CGp+(1-Av)Cas. Since Ay is close to unity Cn will be approximately given by Cn= CGp. The source-follower input capacitance can, however, be reduced below Cap by a bootstrapping circuit in which the drain voltage is made to follow the gate voltage. Let's consider a representative example in which CGp=5 PF, and let the signal-source output resistance be r1= 100 kQ2. The input circuit is in the form of a simple RC low-pass network. The RC time constant is τ=[R。lR。l·Cn=R1·C≡R1·CcD Thus t= 100 k. 5 pF=500 ns=0.5 Us. The corresponding 3-dB or half-power frequency is fH= 1/(2 t) 318 kHz. If R1=1 MQ, the 3-dB frequency will be down to about 30 kHz. Thus we see indeed the limitation on the frequency response that is due to the input capacitance Frequency and Time-Domain Response Small-Signal CS Model for High-Frequency Response We will now consider the frequen time-domain response of the JFET CS amplifier. In Fig. 24.18 an ac representation of a CS amplifier is shown, the dc biasing not being shown. In Fig. 24.19 the JFET small-signal ac equivalent circuit model is shown including the junction capacitances CGs and CGp. The gate-to-drain capacitance Cap is a feedback capacitance in that it is connected between output(drain)and input(gate). Using c 2000 by CRC Press LLC
© 2000 by CRC Press LLC Source-Follower Examples Let’s consider an example of a JFET with IDSS = 10 mA and VP = –4 V. Let VDD = +20 V and IDSQ = IDSS /2 = 5 mA. For IDS = IDSS /2 the value of VGS is –1.17 V. To bias the JFET in the middle of the active region, we will let VGQ = VDD /2 = +10 V, so VSQ = VGQ – VGS = +10 V – (–1.17 V) = +11.17 V. Thus RS = VS Q /IDSQ = 11.17 V/5 mA = 2.23 kW. The transfer conductance at IDS = 5 mA is 3.54 mS so that rO = 1/gm = 283 W. Since gm RS = 7.9, good bias stability will be obtained. If RL >> RS , then AV @ RS /(rO + RS) = 2.23 kW/(283 W + 2.23 kW) = 0.887. If RL = 1 kW, then Rnet = 690 W, and AV drops to 0.709, and if RL = 300 W, Rnet = 264 W and AV is down to 0.483. A BJT emitter-follower circuit has the same equations for the voltage gain as the FET source follower. For the BJT case, rO = 1/gm = VT /IC, where VT = thermal voltage = kT/q @ 25 mV and IC is the quiescent collector current. For IC = 5 mA, we get rO @ 25 mV/5 mA = 5 W as compared to rO = 283 W for the JFET case at the same quiescent current level. So the emitter follower does have a major advantage over the source follower since it has a much lower output resistance rO and can thus drive very small load resistances with a voltage gain close to unity. For example, with RL = 100 W, we get AV @ 0.26 for the source follower as compared to AV @ 0.95 for the emitter follower. The FET source follower does, however, offer substantial advantages over the emitter follower of a much higher input resistance and a much lower input current. For the case in which a very high-impedance source, up in the megohm range, is to be coupled to a low-impedance load down in the range of 100 W or less, a good combination to consider is that of a cascaded FET source follower followed by a BJT emitter follower. This combination offers the very high input resistance of the source follower and the very low output resistance of the emitter follower. For the source-follower circuit under consideration the input resistance will be Rin = [RG1**RG2] = 10 MW. If the JFET gate current is specified as 1 nA (max), and for good bias stability the change in gate voltage due to the gate current should not exceed *VP*/10 = 0.4 V, the maximum allowable value for [RG1**RG2] is given by IG · [RG1**RG2] < 0.4 V. Thus [RG1**RG2] < 0.4 V/1 nA = 0.4 GW = 400 MW. Therefore RG1 and RG2 can each be allowed to be as large as 800 MW, and very large values for Rin can thus be obtained. At higher frequencies the input capacitance Cin must be considered, and Cin will ultimately limit the input impedance of the circuit. Since the input capacitance of the FET will be comparable to that of the BJT, the advantage of the FET source follower over the BJT emitter follower from the standpoint of input impedance will be obtained only at relatively low frequencies. Source-Follower Frequency Response The input capacitance of the source follower is given by Cin = CGD + (1 – AV)CGS . Since AV is close to unity, Cin will be approximately given by Cin @ CGD. The source-follower input capacitance can, however, be reduced below CGD by a bootstrapping circuit in which the drain voltage is made to follow the gate voltage. Let’s consider a representative example in which CGD = 5 pF, and let the signal-source output resistance be R1 = 100 kW. The input circuit is in the form of a simple RC low-pass network. The RC time constant is t = [RuuRG1uuRG2] · Cin @ R1 · Cin @ R1 · CGD Thus t @ 100 kW · 5 pF = 500 ns = 0.5 ms. The corresponding 3-dB or half-power frequency is fH = 1/(2 pt) = 318 kHz. If R1 = 1 MW, the 3-dB frequency will be down to about 30 kHz. Thus we see indeed the limitation on the frequency response that is due to the input capacitance. Frequency and Time-Domain Response Small-Signal CS Model for High-Frequency Response We will now consider the frequency- and time-domain response of the JFET CS amplifier. In Fig. 24.18 an ac representation of a CS amplifier is shown, the dc biasing not being shown. In Fig. 24.19 the JFET small-signal ac equivalent circuit model is shown including the junction capacitances CGS and CGD. The gate-to-drain capacitance CGD is a feedback capacitance in that it is connected between output (drain) and input (gate). Using
Miller's theorem for shunt feedback this feedback capacitance can 仝VDD be transformed into an equivalent input capacitance CGD'=(1 Av)CGp and an equivalent output capacitance CGp"=(1 1/Av)CGD, as shown in Fig. 24.20. The net input capacitance is now Cin= CGs +(1-Av)Cap and the net output capacitance is Co (1-1/Ay)CGD Cr Since the voltage gain Ay is given by Ay -8m Rnet, where Rnet represents the net load resistance, the equations for Cn and Co can be written approximately as Cn= Cos +(1 8m, Rnet )CGp and Co=[1+ 1/(8m rnet )CGD Cl. Since usually Ay 8m Rnet > 1, Co can be written as CO= CGD+ CL. Note that the FIGURE 24.18 Common-source amplifier voltage gain given by Av =-8m Rnet is not valid in the higher fre- quency, where Ay will decrease with increasing frequency. Therefore the expressions for Cin and Co will not be exact but will still be a CGD useful approximation for the determination of the frequency-and time-domain responses. We also note that the contribution of Cgp to the input capacitance is increased by the Miller effect factor of 1+ gm Rnet The circuit in Fig. 24.21 is in the form of two cascaded RC low- pass networks. The RC time constant on the input side is Tr [R‖Rl·Cn≡R1·Cm, where r1 is the signal- source resistance.The RC time constant on the output side is given by t2=Rnet Co. The FIGURE 24.19 AC small-signal model. corresponding breakpoint frequencies are eCcs+CI-A f=2r12R1·Cm R f 2兀τ FIGURE 24 20 The 3-dB or half-power frequency of this amplifier stage will be function of f and f. If these two breakpoint frequencies are RIllRG separated by at least a decade (i. e, 10: 1 ratio), the 3-dB frequency will be approximately equal to the lower of the two breas eas frequencies. If the breakpoint frequencies are not well separat NE TO then the 3-dB frequency can be obtained from the following approx imate relationship:(1/SdB)=(1/f1)2+(1/f2)2. The time-domain response as expressed in terms of the 10 to 90% rise time is related to the frequency-domain response by the approximate relationship FIGURE 24.21 that tris =0.35/JB We will now consider a representative example. We will let Cas=10 pF and Cgd=5 pE. We will assume that the net load driven by the drain of the transistors is Rnet=2 kQ2 and Ci= 10 pE. The signal-source resistance R,=100 Q2. The JFET will have Ipss =10 mA, Ipso=IDss /2=5 mA, and Vp=-4 V, so 8m=3.535 mS. Thus the midfrequency gain is A =-8m, Ret =-3.535 mS. 2 kQ2=-7.07. Therefore we have that Cm≡Cas+(1+gnRa)CGD=10pF+8.07·5pF=50pF
© 2000 by CRC Press LLC Miller’s theorem for shunt feedback this feedback capacitance can be transformed into an equivalent input capacitance CGD ¢ = (1 – AV)CGD and an equivalent output capacitance CGD ¢¢ = (1 – 1/AV)CG D , as shown in Fig. 24.20. The net input capacitance is now Cin = CGS + (1 – AV)CGD and the net output capacitance is CO = (1 – 1/AV)CGD + CL. Since the voltage gain AV is given by AV = –gm Rnet , where Rnet represents the net load resistance, the equations for Cin and CO can be written approximately as Cin = CGS + (1 + gm Rnet)CGD and CO = [1 + 1/(gm Rnet)]CGD + CL. Since usually AV = gm Rnet >> 1, CO can be written as CO @ CGD + CL . Note that the voltage gain given by AV = –gm Rnet is not valid in the higher frequency, where AV will decrease with increasing frequency. Therefore the expressions for Cin and CO will not be exact but will still be a useful approximation for the determination of the frequency- and time-domain responses. We also note that the contribution of CGD to the input capacitance is increased by the Miller effect factor of 1 + gm Rnet . The circuit in Fig. 24.21 is in the form of two cascaded RC lowpass networks. The RC time constant on the input side is t1 = [R1uuRG] · Cin @ R1 · Cin , where R1 is the signal-source resistance. The RC time constant on the output side is given by t2 = Rnet · CO . The corresponding breakpoint frequencies are and The 3-dB or half-power frequency of this amplifier stage will be a function of f1 and f2. If these two breakpoint frequencies are separated by at least a decade (i.e., 10:1 ratio), the 3-dB frequency will be approximately equal to the lower of the two breakpoint frequencies. If the breakpoint frequencies are not well separated, then the 3-dB frequency can be obtained from the following approximate relationship: (1/f3dB)2 @ (1/f1)2 + (1/f2)2 . The time-domain response as expressed in terms of the 10 to 90% rise time is related to the frequency-domain response by the approximate relationship that trise @ 0.35/f3dB . We will now consider a representative example. We will let CGS = 10 pF and CGD = 5 pF. We will assume that the net load driven by the drain of the transistors is Rnet = 2 kW and CL = 10 pF. The signal-source resistance R1 = 100 W. The JFET will have IDSS = 10 mA, IDSQ = IDSS /2 = 5 mA, and VP = –4 V, so gm = 3.535 mS. Thus the midfrequency gain is AV = –gm Rnet = –3.535 mS · 2 kW = –7.07. Therefore we have that Cin @ CGS + (1 + gm Rnet)CGD = 10 pF + 8.07 · 5 pF = 50.4 pF and CO @ CGD + CL = 15 pF FIGURE 24.18 Common-source amplifier. FIGURE 24.19 AC small-signal model. FIGURE 24.20 FIGURE 24.21 f R C 1 1 1 1 2 1 2 = = pt p × in f R C 2 2 1 2 1 2 = = pt p × net O
Thus T,=R, Cin =100 Q2. 50.4 pF=5040 ps= 5.04 ns, and t2=Rnet. Co=2 kQ2 15 PF=30 ns. The corresponding breakpoint frequencies are f= 1/(2T. 5.04 ns)=31.6 MHz and f2=1/(2T. 30 ns)=5.3 MHz. The 3-dB frequency of the amplifier can be obtained from(1/B)2=(1/f1)2+(1/f)2=(1/31.6 MHz) 2 (1/5.3 MHz)2, which gives dB 5.2 MHz. The 10 to 90% rise time can be obtained from trise =0.35/dB 035/5.2MHz=67ns. In the preceding example the dominant time constant is the output circuit time constant of T2=30 ns due to the combination of load resistance and output capacitance. If we now consider a signal-source resistance of I kQ, the input circuit time constant will be T,=R, Cin=1000 Q2. 50.4 PF= 50.4 ns. The corresponding =1/(2·504 3. 16 MHz and f= 1/(2T 30 ns)=5.3 MHz. The 3-dB frequency is now sdB 2.7 MHz, and the rise time is frise 129 ns. If R, is further increased to 10 kQ, we obtain T=RI. Cin=10 kQ2. 50.4 pF= 504 ns, giving breakpoint frequencies of f= 1/(2T 504 ns)=316 kHz and f=1/(2T 30 ns)=5.3 MHz. Now t, is clearly the dominant time constant, the 3-dB frequency is now down fAdB≡f=316kHz,and me is up to trise= 1. 1 As. Finally, for the case of R, frequency will be only 3. 16 kHz and the rise time will be 111 us Use of Source Follower for Impedance Transformation We see that large values of signal-source resistance can seriously limit the amplifier bandwidth and increase the rise time. In these cases, the use of an impedance transforming circuit such as an FET source fol lower or a B]T emitter follower can be very useful. Let's consider the cci Q2s yC2 use of a source follower as shown in Fig. 24.22. We will assume that + both FETs are identical to the one in the preceding examples and are biased at Ipso =5 mA. The source follower Q, will have an input capacitance of Cin= CGD+(1- Av)Cos= Cgd=5 pE, since Ay will be very close to unity for a source follower that is driving a CS amplifier. The source-follower output resistance will be To= 1/gm= 1/3.535 ms FIGURE 24. 22 283Q2. Let's again consider the case of R,=1 MQ2. The time constant due to the combination of R, and the input capacitance of the source follower is TsF=1 MQ2. 5 pf =5 us. The time constant due to the combination of the source-follower output resistance ro and the input capacitance of Cin=283 Q2. 50.4 PF= 14 ns, and the time constant of the output circuit is T2=30 ns, as before. The breakpoint frequencies are sF=31.8 kHz, f=11 MHz, and f2=5.3 MHZ. The 3-dB frequency of the system is now B = sE=31.8 kHz, and the rise time is trise= 11 us. The use of the source follower thus results in an improvement by a factor of 10: 1 over the preceding circuit Voltage- Variable resistor Operation of a JFEt as a Voltage- Variable Resistor We will now consider the operation of a JFET as a voltage-variable resistor(VVR). A JFET can be used as a vvR in which the drain-to- GS --IV arce resistance Ta, of the JFET can be varied by variation of VGs. For values of Vps<< Vp the Ips vs. Vps characteristics are approximately linear, so the JFET looks like a resistor, the resistance value of which CtvGs-2v can be varied by the gate voltage as shown in Fig. 24.23 YGs2-3v The channel conductance in the region where Vps < Vp is given by gas Ao/L= WHo/L, where the channel height H is given by H Ho-2Wp. In this equation Wp is the depletion region width and Ho is the value of H as Wp-0. The depletion region width is given by Wp=kV,= kVas+o, where K is a constant, FIGURE 24.23 the junction voltage, and d is the pn-junction contact potential (typically around 0.8 to 1.0V). As Vas increases, Wp increases and the channel height H decreases as given by H=Ho-2KIas+ When Vos=Vp, the channel is completely pinched off, so H=0 and thus 2K/Vp+=Ho Therefore 2K Ho/Vp+o, and thus c 2000 by CRC Press LLC
© 2000 by CRC Press LLC Thus t1 = R1 · Cin = 100 W · 50.4 pF = 5040 ps = 5.04 ns, and t2 = Rnet · CO = 2 kW · 15 pF = 30 ns. The corresponding breakpoint frequencies are f1 = 1/(2p · 5.04 ns) = 31.6 MHz and f2 = 1/(2p · 30 ns)= 5.3 MHz. The 3-dB frequency of the amplifier can be obtained from (1/f3dB)2 @ (1/f1)2 + (1/f2)2 = (1/31.6 MHz)2 + (1/5.3 MHz)2 , which gives f3dB @ 5.2 MHz. The 10 to 90% rise time can be obtained from trise @ 0.35/f3dB = 0.35/5.2 MHz = 67 ns. In the preceding example the dominant time constant is the output circuit time constant of t2 = 30 ns due to the combination of load resistance and output capacitance. If we now consider a signal-source resistance of 1 kW, the input circuit time constant will be t1 = R1 · Cin = 1000 W · 50.4 pF = 50.4 ns. The corresponding breakpoint frequencies are f1 = 1/(2p · 50.4 ns) = 3.16 MHz and f2 = 1/(2p · 30 ns) = 5.3 MHz. The 3-dB frequency is now f3dB @ 2.7 MHz, and the rise time is trise @ 129 ns. If R1 is further increased to 10 kW, we obtain t1 = R1 · Cin = 10 kW · 50.4 pF = 504 ns, giving breakpoint frequencies of f1 = 1/(2p · 504 ns) = 316 kHz and f2 = 1/(2p · 30 ns) = 5.3 MHz. Now t1 is clearly the dominant time constant, the 3-dB frequency is now down to f3dB @ f1 = 316 kHz, and the rise time is up to trise @ 1.1 ms. Finally, for the case of R1 = 1 MW, the 3-dB frequency will be only 3.16 kHz and the rise time will be 111 ms. Use of Source Follower for Impedance Transformation We see that large values of signal-source resistance can seriously limit the amplifier bandwidth and increase the rise time. In these cases, the use of an impedance transforming circuit such as an FET source follower or a BJT emitter follower can be very useful. Let’s consider the use of a source follower as shown in Fig. 24.22. We will assume that both FETs are identical to the one in the preceding examples and are biased at IDSQ = 5 mA. The source follower Q1 will have an input capacitance of Cin = CGD + (1 – AV1)CGS @ CGD = 5 pF, since AV will be very close to unity for a source follower that is driving a CS amplifier. The source-follower output resistance will be rO = 1/gm = 1/3.535 mS = 283 W. Let’s again consider the case of R1 = 1 MW. The time constant due to the combination of R1 and the input capacitance of the source follower is tSF = 1 MW · 5 pf = 5 ms. The time constant due to the combination of the source-follower output resistance rO and the input capacitance of the CS stage is t1 = rO · Cin = 283 W · 50.4 pF = 14 ns, and the time constant of the output circuit is t2 = 30 ns, as before. The breakpoint frequencies are fSF = 31.8 kHz, f1 = 11 MHz, and f2 = 5.3 MHz. The 3-dB frequency of the system is now f3dB @ fSF = 31.8 kHz, and the rise time is trise @ 11 ms. The use of the source follower thus results in an improvement by a factor of 10:1 over the preceding circuit. Voltage-Variable Resistor Operation of a JFET as a Voltage-Variable Resistor We will now consider the operation of a JFET as a voltage-variable resistor (VVR). A JFET can be used as a VVR in which the drain-tosource resistance rds of the JFET can be varied by variation of VGS . For values of VDS << VP the IDS vs. VDS characteristics are approximately linear, so the JFET looks like a resistor, the resistance value of which can be varied by the gate voltage as shown in Fig. 24.23. The channel conductance in the region where VDS << VP is given by gds = As/L = WHs/L, where the channel height H is given by H = H0 – 2WD. In this equation WD is the depletion region width and H0 is the value of H as WD Æ 0. The depletion region width is given by WD =K = K , where K is a constant, VJ is the junction voltage, and f is the pn-junction contact potential (typically around 0.8 to 1.0 V).As VGS increases,WD increases and the channel height H decreases as given by H = H0 – 2K . When VGS = VP , the channel is completely pinched off, so H = 0 and thus 2K = H0. Therefore 2K = H0 / , and thus FIGURE 24.22 FIGURE 24.23 VJ VGS + f VGS + f VP + f VP + f
THE INVENTION OF THE TRANSISTOR n 1907, the American Telephone and Telegraph Company(AT&T)and the Western Electric Company combined their engineering depar ments and established the Bell Telephone Laboratory on West Street in New York City. By 1921, the labo- ratories constituted the largest industrial research organization in the country, 00,000 square feet in a 13-story building in lower Manhattan and employing more than 1500 men and women. The organization was put on a more formal footing in 1925, when Frank B Jewett was made President of Bell Telephone Laboratories, Inc. In the following decades, the labs distinguished themselves by contri- butions not only to communications technology, but to basic science as well. The awarding of the nobel Prize in Physics to Clinton J. Davisson in 1937 wa simply the most prominent recognition of the labo- The first point-contact transistor t Bell Labs The true importance of the fusion of science and in 1947 by John Bardeen, will 三二 nd walter engineering in the industrial laboratory was made Brattain, had a thin gold foil along polysty apparent to all in the years after World War II. In rene triangle. The foil was slit at s apex and 1947, three Bell Labs physicist-engineers produced was pressed against a piece of germanium by he metal the single most significant electronic invention of the piece at the top of the photo( Photo courtesy of AT&T a-the transistor. John Bardeen, Walter Brattain, Bell Laboratories. and William Shocklet ciously seeking exploit new technology about the behavior of semiconducting materials when they devised a way to make a crystal of germanium do the work of a triode vacuum tube, the most basic of electronic components H=H。-H Hol l Vp +o When VGs=0, the channel is fully open or"on, " and L
© 2000 by CRC Press LLC For gds we now have When VGS = 0, the channel is fully open or “on,” and HH H V V H V V GS P GS P = - + + = - + + Ê Ë Á ˆ ¯ 00 0 ˜ 1 f f f f g WH L WH L V V ds GS P == - + + Ê Ë Á ˆ ¯ ˜ s s f f 0 1 g g WH L V ds ds P == - + Ê Ë Á Á ˆ ¯ ˜ ˜ (on) s f f 0 1 THE INVENTION OF THE TRANSISTOR n 1907, the American Telephone and Telegraph Company (AT&T) and the Western Electric Company combined their engineering departments and established the Bell Telephone Laboratory on West Street in New York City. By 1921, the laboratories constituted the largest industrial research organization in the country, occupying 400,000 square feet in a 13-story building in lower Manhattan and employing more than 1500 men and women. The organization was put on a more formal footing in 1925, when Frank B. Jewett was made President of Bell Telephone Laboratories, Inc. In the following decades, the labs distinguished themselves by contributions not only to communications technology, but to basic science as well. The awarding of the Nobel Prize in Physics to Clinton J. Davisson in 1937 was simply the most prominent recognition of the laboratories’ scientific work. The true importance of the fusion of science and engineering in the industrial laboratory was made apparent to all in the years after World War II. In 1947, three Bell Labs physicist-engineers produced the single most significant electronic invention of the era—the transistor. John Bardeen, Walter Brattain, and William Shockley were consciously seeking to exploit new technology about the behavior of semiconducting materials when they devised a way to make a crystal of germanium do the work of a triode vacuum tube, the most basic of electronic components. I The first point-contact transistor developed at Bell Labs in 1947 by John Bardeen, William Shockley, and Walter Brattain, had a thin gold foil along the sides of a polystyrene triangle. The foil was slit at the triangle’s apex and was pressed against a piece of germanium by the metal piece at the top of the photo (Photo courtesy of AT&T Bell Laboratories.)