《电子工程师手册》学习资料（英文版）chapter 24 Transistors.pdf

24 Transistors 24.1 Junction Field-Effect Transistors FET Biasing. Transfer Characteristics. JFET Outpu Resistance. Source Follower. Frequency and Time-Domain Response. Voltage-Variable Resistor 24.2 Bipolar Transistors Biasing the Bipolar Transistor. Small-Signal Operation. A Small Signal Equivalent Circuit. Low-Frequency Performance. The Emitter-Follower or Common-Collector(CC) Circuit. The Sidney Soclof Common-Emitter Bypass Capacitor CE. High-Frequency California State University Response. Complete Response. Design Comments. Integrated Circuits. The Degenerate Common-Emitter Stage. The Difference Amplifier. The Current Mirror. The Difference Stage with Current Joseph Watson Mirror Biasing. The Current Mirror as a load University of Wales, Swansea 24.3 The Metal-Oxide Semiconductor Field-Effect (MOSFET) John R. Brews Current-Voltage Characteristics. Important Device The University of arizona Parameters. Limitations upon Miniaturization 24.1 Junction Field-Effect Transistors A junction field-effect transistor, or JFET, is a type of transistor in which the current flow through the device between the drain and source electrodes is controlled by the voltage applied to the gate electrode. a simple physical model of the JFET is shown in Fig. 24. 1. In this JFET an n-type conducting channel exists between drain and source. The gate is a p* region that surrounds the n-type channel. The gate-to-channel pn junction is normally kept reverse-biased. As the reverse bias voltage between gate and channel increases, the depletion region width increases, as shown in Fig. 24.2. The depletion region extends mostly into the n-type channel because of the heavy doping on the p+ side. The depletion region is depleted of mobile charge carriers and thus cannot contribute to the conduction of current between drain and source. Thus as the gate voltage increases, he cross-sectional areas of the n-type channel available for current flow decreases. This reduces the current flow between drain and source. As the gate voltage increases, the channel gets further constricted, and the current flow gets smaller. Finally when the depletion regions meet in the middle of the channel, as shown in Fig 24.3, the channel is pinched off in its entirety between source and drain. At this point the current flow between drain and source is reduced to essentially zero. This voltage is called the pinch-off voltage, Vp. The inch-off voltage is also represented by Vas (off)as being the gate-to-source voltage that turns the drain-to- source current Ips off. We have been considering here an n-channel JFET. The complementary device is the p-channel JFET that has an t gate region surrounding a p-type channel. The operation of a p-channel JFET is the same as for an n-channel device, except the algebraic signs of all dc voltages and currents are reversed We have been considering the case for Vos small compared to the pinch-off voltage such that the channel sentially uniform from drain to source, as shown in Fig. 24. 4(a). Now let's see what happens as Vos increases As an example let's assume an n-channel JFET with a pinch-off voltage of Vp=-4 V. we will see what happens C 2000 by CRC Press LLC

© 2000 by CRC Press LLC 24 Transistors 24.1 Junction Field-Effect Transistors JFET Biasing • Transfer Characteristics • JFET Output Resistance • Source Follower • Frequency and Time-Domain Response • Voltage-Variable Resistor 24.2 Bipolar Transistors Biasing the Bipolar Transistor • Small-Signal Operation • A SmallSignal Equivalent Circuit • Low-Frequency Performance • The Emitter-Follower or Common-Collector (CC) Circuit • The Common-Emitter Bypass Capacitor CE • High-Frequency Response • Complete Response • Design Comments • Integrated Circuits • The Degenerate Common-Emitter Stage • The Difference Amplifier • The Current Mirror • The Difference Stage with Current Mirror Biasing • The Current Mirror as a Load 24.3 The Metal-Oxide Semiconductor Field-Effect Transistor (MOSFET) Current-Voltage Characteristics • Important Device Parameters • Limitations upon Miniaturization 24.1 Junction Field-Effect Transistors Sidney Soclof A junction field-effect transistor, or JFET, is a type of transistor in which the current flow through the device between the drain and source electrodes is controlled by the voltage applied to the gate electrode. A simple physical model of the JFET is shown in Fig. 24.1. In this JFET an n-type conducting channel exists between drain and source. The gate is a p+ region that surrounds the n-type channel. The gate-to-channel pn junction is normally kept reverse-biased. As the reverse bias voltage between gate and channel increases, the depletion region width increases, as shown in Fig. 24.2. The depletion region extends mostly into the n-type channel because of the heavy doping on the p+ side. The depletion region is depleted of mobile charge carriers and thus cannot contribute to the conduction of current between drain and source. Thus as the gate voltage increases, the cross-sectional areas of the n-type channel available for current flow decreases. This reduces the current flow between drain and source. As the gate voltage increases, the channel gets further constricted, and the current flow gets smaller. Finally when the depletion regions meet in the middle of the channel, as shown in Fig. 24.3, the channel is pinched off in its entirety between source and drain. At this point the current flow between drain and source is reduced to essentially zero. This voltage is called the pinch-off voltage, VP . The pinch-off voltage is also represented by VGS (off) as being the gate-to-source voltage that turns the drain-tosource current IDS off. We have been considering here an n-channel JFET. The complementary device is the p-channel JFET that has an n+ gate region surrounding a p-type channel. The operation of a p-channel JFET is the same as for an n-channel device, except the algebraic signs of all dc voltages and currents are reversed. We have been considering the case for VDS small compared to the pinch-off voltage such that the channel is essentially uniform from drain to source, as shown in Fig. 24.4(a). Now let’s see what happens as VDS increases. As an example let’s assume an n-channel JFET with a pinch-off voltage of VP = –4 V. We will see what happens Sidney Soclof California State University, Los Angeles Joseph Watson University of Wales, Swansea John R. Brews The University of Arizona

PtGATE N-TYPE CHANNEL P+ GATE FIGURE 24.1 、 PT GATE PtGATE N-TYPE CHANNEL FIGURE 24.2 FIGURE 24. 3 for the case of VGs =0 as Vs increases In Fig. 24. 4(a)the situation is shown for the case of Vns=0 in which the JFET is fully""and there is a uniform channel from source to drain. This is at point A on the Ins vs. Vos curve of Fig. 24.5. The drain-to-source conductance is at its maximum value of gs(on), and the drain-to- source resistance is correspondingly at its minimum value of Tas (on). Now let's consider the case of Vns=+l V, shown in Fig. 24.4(b). The gate-to-channel bias voltage at the source end is still VGs=0. The gate-to-channel bias voltage at the drain end is VGp= VGs-Vos=-1 V, so the depletion region will be wider at the drain end of the channel than at the source end. the channel will thus be narrower at the drain end than at the source end, and this will result in a decrease in the channel conductance ga and, correspondingly, an increase in the channel resistance ras. So the slope of the Ips vs. Vos curve that corresponds to the channel conductance will be smaller at Vns=1 V than it was at Vns =0, as shown at point B on the Ips vS. Vrs curve of Fig. 24.5 In Fig. 24.4(c)the situation for Vns =+2 V is shown. The gate-to-channel bias voltage at the source end is still VGs =0, but the gate-to-channel bias voltage at the drain end is now VGp=VGs-Vps=-2V, so the depletion region will now be substantially wider at the drain end of the channel than at the source end. This leads to a further constriction of the channel at the drain end, and this will again result in a decrease in the channel conductance ga and, correspondingly, an increase in the channel resistance ras. So the slope of the Ips vs. Vos urve will be smaller at Vns=2V than it was at Vns=1 V, as shown at point Con the Ips vS Vns curve of Fig. 24 In Fig. 24. 4(d)the situation for Vps =+3 V is shown, and this corresponds to point d on the IIs vs. Vps curve of Fig. 24.5 When Vns=+4 V, the gate-to-channel bias voltage will be VGD=Vo-Vns =0-4V=-4 V= Vp. As a result the channel is now pinched off at the drain end but is still wide open at the source end since VGs=0,as nown in Fig. 24.4(e). It is very important to note that the channel is pinched off just for a very short distance at the drain end so that the drain -to-source current i can still continue to flow this is not at all the same situation as for the case of Vas= Vp, where the channel is pinched off in its entirety, all the way from source to drain. When this happens, it is like having a big block of insulator the entire distance between source and drain, and Ips is reduced to essentially zero. The situation for Vns=+4 V=-Vp is shown at point E on the Ips curve of Fig. 24.5 For Vps >+4 V, the current essentially saturates and doesnt increase much with further increases in Vps. As Vps increases above +4 V, the pinched-off region at the drain end of the channel gets wider, which increases Tas. This increase in ras essentially counterbalances the increase in Vps such that Ips does not increase much This region of the Ins vS. Vps curve in which the channel is pinched off at the drain end is called the active region and is also known as the saturated region. It is called the active region because when the JFET is to be sed as an amplifier, it should be biased and operated in this region. The saturated value of drain current up in the active region for the case of VGs=0 is called the drain saturation current, Ipss(the third subscript S c 2000 by CRC Press LLC

© 2000 by CRC Press LLC for the case of VGS = 0 as VDS increases. In Fig. 24.4(a) the situation is shown for the case of VDS = 0 in which the JFET is fully “on” and there is a uniform channel from source to drain. This is at point A on the IDS vs. VDS curve of Fig. 24.5. The drain-to-source conductance is at its maximum value of gds (on), and the drain-tosource resistance is correspondingly at its minimum value of rds (on). Now let’s consider the case of VDS = +1 V, as shown in Fig. 24.4(b). The gate-to-channel bias voltage at the source end is still VGS = 0. The gate-to-channel bias voltage at the drain end is VGD = VGS –VDS = –1 V, so the depletion region will be wider at the drain end of the channel than at the source end. The channel will thus be narrower at the drain end than at the source end, and this will result in a decrease in the channel conductance gds and, correspondingly, an increase in the channel resistance rds . So the slope of the IDS vs. VDS curve that corresponds to the channel conductance will be smaller at VDS = 1 V than it was at VDS = 0, as shown at point B on the IDS vs. VDS curve of Fig. 24.5. In Fig. 24.4(c) the situation for VDS = +2 V is shown. The gate-to-channel bias voltage at the source end is still VGS = 0, but the gate-to-channel bias voltage at the drain end is now VGD = VGS – VDS = –2 V, so the depletion region will now be substantially wider at the drain end of the channel than at the source end. This leads to a further constriction of the channel at the drain end, and this will again result in a decrease in the channel conductance gds and, correspondingly, an increase in the channel resistance rds . So the slope of the IDS vs. VDS curve will be smaller at VDS = 2 V than it was at VDS = 1 V, as shown at point C on the IDS vs.VDS curve of Fig. 24.5. In Fig. 24.4(d) the situation for VDS = +3 V is shown, and this corresponds to point D on the IDS vs. VDS curve of Fig. 24.5. When VDS = +4 V, the gate-to-channel bias voltage will be VGD = VGS – VDS = 0 – 4 V = –4 V = VP . As a result the channel is now pinched off at the drain end but is still wide open at the source end since VGS = 0, as shown in Fig. 24.4(e). It is very important to note that the channel is pinched off just for a very short distance at the drain end so that the drain-to-source current IDS can still continue to flow. This is not at all the same situation as for the case of VGS = VP , where the channel is pinched off in its entirety, all the way from source to drain. When this happens, it is like having a big block of insulator the entire distance between source and drain, and IDS is reduced to essentially zero. The situation for VDS = +4 V = –VP is shown at point E on the IDS vs. VDS curve of Fig. 24.5. For VDS > +4 V, the current essentially saturates and doesn’t increase much with further increases in VDS . As VDS increases above +4 V, the pinched-off region at the drain end of the channel gets wider, which increases rds . This increase in rds essentially counterbalances the increase in VDS such that IDS does not increase much. This region of the IDS vs. VDS curve in which the channel is pinched off at the drain end is called the active region and is also known as the saturated region. It is called the active region because when the JFET is to be used as an amplifier, it should be biased and operated in this region. The saturated value of drain current up in the active region for the case of VGS = 0 is called the drain saturation current, IDSS (the third subscript S FIGURE 24.1 FIGURE 24.2 FIGURE 24.3

ne basic requirement is that the gate-to-channel bias voltage at the drain end of the channel,Vp, be greater than the pinch-off voltage ipss Ve For the example under consideration with Vp=-4 V, this means Vos -Vs 2+4V. Thus, for Vas =0, the active region will begin at D Vps=+4 V When VG =-1 V, the active region will begin at Vps -3v +3V, for now VGd=-4 V. when VGs =-2 V, the active region begins -Av at Vos =+2 V, and when Vos=-3V, the active region begins at Vps +1V. The dotted line in Fig. 24.6 marks the boundary between the nonsaturated and active regions. FIGURE 24.6 The upper boundary of the active region is marked by the onset of the avalanche breakdown of the gate-to-channel pn junction. When Vos=0, this occurs at Vp Since Vog= Vns- VGs and breakdown occurs when Vxg= BVpg, as Vos increases the breakdown voltage decreases, as given by BVDG= BVos-VGs. Thus BVms= BVD+ VGs. For example, if the gate-to-channel breakdown volta is 50 V, the Vos breakdown voltage will start off at 50 V when Vo=0 but decrease to 46V when Va=-4V. In the nonsaturated region Ins is a function of both Vas and Vps and in the lower portion of the nonsaturated region where Vos is small compared to Vp, Ips becomes an approximately linear function of Vps. This linear portion of the nonsaturated is called the voltage-variable resistance(VvR)region, for in this region the JFET acts like a linear resistance element between source and drain The resistance is variable in that it is controlled by the gate voltage. This region and VvR application will be discussed in a later section. The JFET can also be operated in this region as a switch, and this will also be discussed in a later section JFET Biasing Voltage Source Biasing Now we will consider the biasing of JFETs for operation in the active region. The simplest biasing method is shown in Fig. 24.7, in which a voltage source VaG is used to provide the quiescent gate-to-source bias voltage VGso In the active region the transfer equation for the JFET has been given as Ins=Ipss[1-(VGs/Vp))2,so for a quiescent drain current of Ipso the corresponding gate voltage will be given by Voso=Vp (1- Ioso/Ipss. For a Q point in the middle of the active region, we have that Ipso= Ipss/2, so VGso=Vp(1-/1/2)=0.293 Vp VGG= The voltage source method of biasing has several major drawbacks. Since Vp ill have the opposite polarity of the drain supply voltage Vop, the gate bias voltag will require a second power supply. For the case of an n-channel JFET, Vpp FIGURE 24.7 Voltage come from a positive supply voltage and VGG must come from a separate negative source biasing power supply voltage or battery. A second, and perhaps more serious, problem is the"open-loop"nature of this biasing method. The JFET parameters of Ipps and p will exhibit very substantial unit-to-unit variations, often by as much as a 2: 1 factor. There is also a significant temperature dependence of Ipos and Vp. These riations will lead to major shifts in the position of the Q point and the resulting DIPs distortion of the signal. A much better biasing method is shown in Fig. 24.8 Self Biasing RG Rs Ips.Rs The biasing circuit of Fig 24.8 is called a self-biasing circuit in that the gate-to- source voltage is derived from the voltage drop produced by the flow of drain current through the source biasing resistor Rs. It is a closed-loop system in that variations in the JFET parameters can be partially compensated for by the biasing FIGURE 24.8 Self-biasing circuit. The gate resistor R is used to provide a dc return path for the gate leakage current and is generally up in the megohm range. The voltage drop across Rs is given by Vs= Ips. Rs. The voltage drop across the gate resistor RG is VG=IG RG. Since IG is usually in the low nanoampere or even picoampere range, as long as RG is not extremely large c 2000 by CRC Press LLC

© 2000 by CRC Press LLC the basic requirement is that the gate-to-channel bias voltage at the drain end of the channel, VGD , be greater than the pinch-off voltage VP . For the example under consideration with VP = –4 V, this means that VGD = VGS – VDS must be more negative than –4 V. Therefore, VDS – VGS ³ +4 V. Thus, for VGS = 0, the active region will begin at VDS = +4 V. When VGS = –1 V, the active region will begin at VDS = +3 V, for now VGD = –4 V. When VGS = –2 V, the active region begins at VDS = +2 V, and when VGS = –3 V, the active region begins at VDS = +1 V. The dotted line in Fig. 24.6 marks the boundary between the nonsaturated and active regions. The upper boundary of the active region is marked by the onset of the avalanche breakdown of the gate-to-channel pn junction. When VGS = 0, this occurs at VDS = BVDS = BVDG. Since VDG = VDS – VGS and breakdown occurs when VDG = BVDG , as VGS increases the breakdown voltage decreases, as given by BVDG = BVDS – VGS . Thus BVDS = BVDG + VGS. For example, if the gate-to-channel breakdown voltage is 50 V, the VDS breakdown voltage will start off at 50 V when VGS = 0 but decrease to 46 V when VGS = –4 V. In the nonsaturated region IDS is a function of both VGS and VDS, and in the lower portion of the nonsaturated region where VDS is small compared to VP , IDS becomes an approximately linear function of VDS . This linear portion of the nonsaturated is called the voltage-variable resistance (VVR) region, for in this region the JFET acts like a linear resistance element between source and drain. The resistance is variable in that it is controlled by the gate voltage. This region and VVR application will be discussed in a later section. The JFET can also be operated in this region as a switch, and this will also be discussed in a later section. JFET Biasing Voltage Source Biasing Now we will consider the biasing of JFETs for operation in the active region. The simplest biasing method is shown in Fig. 24.7, in which a voltage source VGG is used to provide the quiescent gate-to-source bias voltage VGSQ . In the active region the transfer equation for the JFET has been given as IDS = IDSS [1 – (VGS /VP)]2 , so for a quiescent drain current of IDSQ the corresponding gate voltage will be given by VGSQ = VP (1 – . For a Q point in the middle of the active region, we have that IDSQ = IDSS /2, so VGSQ = VP (1 – ) = 0.293 VP . The voltage source method of biasing has several major drawbacks. Since VP will have the opposite polarity of the drain supply voltage VDD, the gate bias voltage will require a second power supply. For the case of an n-channel JFET, VDD will come from a positive supply voltage and VGG must come from a separate negative power supply voltage or battery. A second, and perhaps more serious, problem is the “open-loop” nature of this biasing method. The JFET parameters of IDDS and VP will exhibit very substantial unit-to-unit variations, often by as much as a 2:1 factor. There is also a significant temperature dependence of IDDS and VP . These variations will lead to major shifts in the position of the Q point and the resulting distortion of the signal. A much better biasing method is shown in Fig. 24.8. Self-Biasing The biasing circuit of Fig. 24.8 is called a self-biasing circuit in that the gate-tosource voltage is derived from the voltage drop produced by the flow of drain current through the source biasing resistor RS . It is a closed-loop system in that variations in the JFET parameters can be partially compensated for by the biasing circuit. The gate resistor RG is used to provide a dc return path for the gate leakage current and is generally up in the megohm range. The voltage drop across RS is given by VS = IDS · RS . The voltage drop across the gate resistor RG is VG = IG · RG. Since IG is usually in the low nanoampere or even picoampere range, as long as RG is not extremely large FIGURE 24.6 FIGURE 24.7 Voltage source biasing. FIGURE 24.8 Self-biasing. IDSQ IDSS § 1 § 2