example, if Ipss=10 mA and Vp=-4V, and for a Q point in the middle of the active region with loso osre o ne voltage drop across RG can be neglected, So VG=0. Thus, we have that VGs= VG-Vs=-Vs=-Ins Rs Fo 5 mA, we have that VGso=0. 293Vp=-1. 17 V. Therefore the required value for the source biasing resistor given by Rs=-VGs /Ipso=1. 17 v/5 mA =234 Q2. This produces a more stable quiescent point than voltage source biasing, and no separate negative power supply is required The closed-loop nature of this biasing circuit can be seen by noting that if changes in the JFET parameters were to cause Ips to increase, the voltage drop across Rs would also increase. This will produce an increase in VGs(in the negative direction for an n-channel JFET), which will act to reduce the increase in Ips. Thus the net increase in Ins will be less due to the feedback voltage drop produced by the flow of Ins through Rs. The same basic action would, of course, occur for changes in the jFET parameters that would cause Ips to decre Bias Stability Now let,s examine the stability of the Q point. We will start again with the basic transfer equation as given by Ips= Ipss[1-(VGs/Vp)]2. From this equation the change in the drain current, AIps, due to changes in Ipss Vos, and Vp can be written as △vp+△lbs Since Vos=-ls·Rs,△vas=-R3·△lns, we obtain that gnR△ △Vp+ Collecting terms in AIps on the left side gives S (1+8nRs)=-8 From this we see that the shift in the quiescent drain current, Alps, is reduced by the presence of Rs by a factor If I /2, then DsSS √Is:2l 2√2I Since VGs=0.293Vp, the source biasing resistor will be rs =-VGs /Ips=-0.293 Vp/Ips. Thus 2√2Ins-0.293Vp 2√2×0.293=0.83 so 1+ 8m Rs=1.83. Thus the sensitivity of Ips due to changes in Vp and Ipss is reduced by a factor of 1.83
© 2000 by CRC Press LLC the voltage drop across RG can be neglected, so VG @ 0. Thus, we have that VGS = VG – VS @ –VS = –IDS · RS . For example, if IDSS = 10 mA and VP = –4 V, and for a Q point in the middle of the active region with IDSQ = IDS S /2 = 5 mA, we have that VGSQ = 0.293VP = –1.17 V. Therefore the required value for the source biasing resistor is given by RS = –VGS /IDSQ = 1.17 V/5 mA = 234 W. This produces a more stable quiescent point than voltage source biasing, and no separate negative power supply is required. The closed-loop nature of this biasing circuit can be seen by noting that if changes in the JFET parameters were to cause IDS to increase, the voltage drop across RS would also increase. This will produce an increase in VGS (in the negative direction for an n-channel JFET), which will act to reduce the increase in IDS . Thus the net increase in IDS will be less due to the feedback voltage drop produced by the flow of IDS through RS . The same basic action would, of course, occur for changes in the JFET parameters that would cause IDS to decrease. Bias Stability Now let’s examine the stability of the Q point. We will start again with the basic transfer equation as given by IDS = IDSS [1 – (VGS /VP)]2 . From this equation the change in the drain current, DIDS , due to changes in IDSS , VGS , and VP can be written as Since VGS = –IDS · RS , DVGS = –RS · DIDS , we obtain that Collecting terms in DIDS on the left side gives Now solving this for DIDS yields From this we see that the shift in the quiescent drain current, DIDS , is reduced by the presence of RS by a factor of 1 + gm RS . If IDS = IDSS /2, then Since VGS = 0.293VP , the source biasing resistor will be RS = –VG S /IDS = –0.293 VP /IDS . Thus so 1 + gm RS = 1.83. Thus the sensitivity of IDS due to changes in VP and IDSS is reduced by a factor of 1.83. DD D D I gV g V V V I I I DS m GS m GS P P DS DSS =- + DSS D D DD I gR I g V V V I I I DS m S DS m GS P P DS DSS =- - + DSS D DD I gR g V V V I I I DS m S m GS P P DS DSS DSS ( ) 1 + =- + D D D I gV V V I I I g R DS m GS P P DS DSS DSS m S = - + + ( ) / 1 g I I V I I V I V m DS DSS P DS DS P DS P = × - = × - = - 2 22 2 2 g R I V V I m S DS P P DS = - ¥ - =¥ = 2 2 0 293 2 2 0 293 0 83 . .
VDD SVDD RG2 Rs IDs.Rs RG RsSIDsRs FIGURE 24.9 FIGURE 24.10 FIGURE 24.11 Transfer characteristi The equation for AIos can now be written in the following form for the fractional change in Ips △IDs-=0.83AV/Vp)+14△ Ipss/lpss 1.83 so Alps/Ips=-045AVp/Vp)+0.77(Alpss/Ipss), and thus a 10% change in Vp will result in approximately a 4.5% change in Ips, and a 10% change in Ipss will result in an 8%change in Ins. Thus, although the situation is improved with the self-biasing circuit using Rs, there will still be a substantial variation in the quiescent current with changes in the JFET parameters A further improvement in bias stability can be obtained by the use of the biasing methods of Figs. 24.9 and 4. 10. In Fig. 24.9 a gate bias voltage VaG is obtained from the Vpp supply voltage by means of the RG-Ra2 voltage divider. The gate-to-source voltage is now VGs=VG-Vs= VGG-IpsRs. So now for Rs we have Rs (VGG-VGs)/Ips. Since Vas is of opposite polarity to VGG, this will result in a larger value for Rs than before. This in turn will result in a larger value for the gm rs product and hence improved bias stability. If we continue with the preceding examples and now let VGG= Vpp/2=+10 V, we have that Rs=(VGG-vgs)Ips [+10V-(1.17V)]/5 mA= 2.234 kQ2, as compared to Rs=234 Q2 that was obtained before. For gm we have gmt 2/ Ios. IDss/(-Vp)=3.54 mS, so 8m Rs=3.54 mS. 2.234 kQ2=7.90. Since 1+ 8mRs=8.90, we now have an improvement by a factor of 8.9 over the open-loop voltage source biasing and by a factor of 4.9 over the self biasing method without the Vog biasing of the gate. Another biasing method that can lead to similar results is the method shown in Fig. 24.10. In this method the bottom end of the source biasing resistor goes to a negative supply voltage Vss instead of to ground. The gate-to-source bias voltage is now given by VGs= VG-Vs=0-(Ips. Rs Vss)so that for Rs we now have Rs Vos- Vss)/Ips. If Vss =-10V, and as before Ips =5 mA and VGs =-1 17V, we have Rs=11.7v/5 mA 2.34 kQ2, and thus gm Rs=7.9 as in the preceding example. So this method does indeed lead to results similar 10% change in Vp will be only 0.9%, and the change in Ips due to a 10% change in IDss will be only 16% to that for the Rs and VGg combination biasing. With either of these two methods the change in Ips due to a The biasing circuits under consideration here can be applied directly to the common-source(CS)amplifier configuration, and can also be used for the common-drain(CD), or source-follower, and common-gate(CG) Transfer Characteristics Transfer Equation ow we will consider the transfer characteristics of the JFET, which is a graph of the output current Ips vS the input voltage VGs in the active region. In Fig. 24. 11 a transfer characteristic curve for a JFET with Vp=-4 V and Ipss =+10 mA is given. This is approximately a square-law relationship as given by Ips=Ipss[1-(VGs/Vp) This equation is not valid for VGs beyond Ve (i.e, VGs< Vp), for in this region the channel is pinched off and c 2000 by CRC Press LLC
© 2000 by CRC Press LLC The equation for DIDS can now be written in the following form for the fractional change in IDS : so DID S /IDS = –0.45 (DVP /VP) + 0.77 (DIDS S /IDSS), and thus a 10% change in VP will result in approximately a 4.5% change in IDS , and a 10% change in IDSS will result in an 8% change in IDS . Thus, although the situation is improved with the self-biasing circuit using RS , there will still be a substantial variation in the quiescent current with changes in the JFET parameters. A further improvement in bias stability can be obtained by the use of the biasing methods of Figs. 24.9 and 24.10. In Fig. 24.9 a gate bias voltage VGG is obtained from the VDD supply voltage by means of the RG1–RG2 voltage divider. The gate-to-source voltage is now VGS = VG – VS = VGG – IDSRS . So now for RS we have RS = (VGG – VGS)/IDS . Since VGS is of opposite polarity to VGG, this will result in a larger value for RS than before. This in turn will result in a larger value for the gm RS product and hence improved bias stability. If we continue with the preceding examples and now let VGG = VDD /2 = +10 V, we have that RS = (VGG – VGS)/IDS = [+10V –(–1.17V)]/5 mA = 2.234 kW, as compared to RS = 234 W that was obtained before. For gm we have gm = = 3.54 mS, so gm RS = 3.54 mS · 2.234 kW = 7.90. Since 1 + gm RS = 8.90, we now have an improvement by a factor of 8.9 over the open-loop voltage source biasing and by a factor of 4.9 over the selfbiasing method without the VGG biasing of the gate. Another biasing method that can lead to similar results is the method shown in Fig. 24.10. In this method the bottom end of the source biasing resistor goes to a negative supply voltage VSS instead of to ground. The gate-to-source bias voltage is now given by VGS = VG –VS = 0 – (IDS · RS + VSS) so that for RS we now have RS = (–VGS – VSS)/IDS . If VSS = –10 V, and as before IDS = 5 mA and VGS = –1.17 V, we have RS = 11.7 V/5 mA = 2.34 kW, and thus gm RS = 7.9 as in the preceding example. So this method does indeed lead to results similar to that for the RS and VGG combination biasing. With either of these two methods the change in IDS due to a 10% change in VP will be only 0.9%, and the change in IDS due to a 10% change in IDSS will be only 1.6%. The biasing circuits under consideration here can be applied directly to the common-source (CS) amplifier configuration, and can also be used for the common-drain (CD), or source-follower, and common-gate (CG) JFET configurations. Transfer Characteristics Transfer Equation Now we will consider the transfer characteristics of the JFET, which is a graph of the output current IDS vs. the input voltage VGS in the active region. In Fig. 24.11 a transfer characteristic curve for a JFET with VP = –4 V and IDSS = +10 mA is given. This is approximately a square-law relationship as given by IDS = IDSS [1 – (VG S /VP)]2 . This equation is not valid for VGS beyond VP (i.e., VGS < VP), for in this region the channel is pinched off and IDS @ 0. FIGURE 24.9 FIGURE 24.10 FIGURE 24.11 Transfer characteristic. DI D D I V V I I DS DS P P DSS DSS = -0 83 + 1 41 1 83 . ( ) . ( ) . / / 2 IDS IDSS × –VP § ( )
t VGs=0, Ips= Ipss. This equation and the corresponding transfer curve can actually the gate-to-channel pn junction is forward-biased and the depletion region wid s be extended up to the point where VGs=+.5 V. In the region where 0< VGs<+0.5 gion width leads to a corresponding expansion of the conducting channel and thus (,iN an increase in Ips above Ipss. As long as the gate-to-channel forward bias voltage is less than about 0.5, the pn junction will be essentially"off"and very little gate current v will flow. If VGs is increased much above +0.5 V, however, the gate-to-channel pn junction will turn"on"and there will be a substantial flow of gate voltage IG. This gate FIGURE 24. 12 Effect current will load down the signal source and produce a voltage drop across the signal source resistance, as shown in Fig. 24.12. This voltage drop can cause Vas to be much smaller than the signal source voltage Vin. As Vin increases, VGs will ultimately level off at a forward bias voltage of about +0.7 V, and the signal source will lose control over VGs, and hence over Ips. This can result in severe distortion of the input signal in the form of clipping, and thus this situation should be avoided. Thus, although it is possible to increase Ips above Ipss by allowing the gate-to-channel junction to become forward-biased by a small amount($0.5 V), the possible benefits are generally far outweighed by the risk of signal distortion. Therefore, JFETs are almost always operated with the gate-to-channel pn junction reverse-biased. Transfer Conductance The slope of the transfer curve, dIps/dVGs, is the dynamic forward transfer conductance, or mutual transfer maximum when IDs=Ipss. Since Ips =Ioss[ 1-(VGs/Vp), 8m can be obtained es as Ips increases, reaching a ductance, 8m. We see that 8m starts off at zero when Vas Vp and increase d we have that 8m=2l √ Insel pss_,ls-I The maximum value of gm is obtained when Vas=0(Ips= Ipss)and is given by gm(VGs=0)=8no=2Ips/(Vp) Small-Signal AC Voltage Gain Let's consider the CS amplifier circuit of Fig 24.13. The input ac signal is DD applied between gate and source, and the output ac voltage is taken between drain and source. Thus the source electrode of this triode device is common to input and output, hence the designation of this JFET configuration as a a good choice of the dc operating point or quiescent point(Q point) or an amplifier is in the middle of the active region at IDs= Ipss/2. This vgG allows for the maximum symmetrical drain current swing, from the qui- escent level of Ipso= Ipss/2, down to a minimum of IDs =0, and up to a maximum of Ips= Ipss. This choice for the Q point is also a good one from FIGURE 24.13 Common-souI the standpoint of allowing for an adequate safety margin for the location amplifier. c 2000 by CRC Press LLC
© 2000 by CRC Press LLC At VGS = 0, IDS = IDSS . This equation and the corresponding transfer curve can actually be extended up to the point where VGS @ +0.5 V. In the region where 0 < VGS < +0.5 V, the gate-to-channel pn junction is forward-biased and the depletion region width is reduced below the width under zero bias conditions. This reduction in the depletion region width leads to a corresponding expansion of the conducting channel and thus an increase in IDS above IDSS . As long as the gate-to-channel forward bias voltage is less than about 0.5 V, the pn junction will be essentially “off” and very little gate current will flow. If VGS is increased much above +0.5 V, however, the gate-to-channel pn junction will turn “on” and there will be a substantial flow of gate voltage IG . This gate current will load down the signal source and produce a voltage drop across the signal source resistance, as shown in Fig. 24.12. This voltage drop can cause VGS to be much smaller than the signal source voltage Vin . As Vin increases, VGS will ultimately level off at a forward bias voltage of about +0.7 V, and the signal source will lose control over VGS , and hence over IDS . This can result in severe distortion of the input signal in the form of clipping, and thus this situation should be avoided. Thus, although it is possible to increase IDS above IDSS by allowing the gate-to-channel junction to become forward-biased by a small amount (£0.5 V), the possible benefits are generally far outweighed by the risk of signal distortion. Therefore, JFETs are almost always operated with the gate-to-channel pn junction reverse-biased. Transfer Conductance The slope of the transfer curve, dID S /dVGS , is the dynamic forward transfer conductance, or mutual transfer conductance, gm . We see that gm starts off at zero when VGS = VP and increases as IDS increases, reaching a maximum when IDS = IDSS . Since IDS = IDSS[1 – (VG S /VP)]2 , gm can be obtained as Since we have that The maximum value of gm is obtained when VGS = 0 (IDS = IDSS) and is given by gm(VGS = 0) = gm0 = 2ID S /(–VP). Small-Signal AC Voltage Gain Let’s consider the CS amplifier circuit of Fig. 24.13. The input ac signal is applied between gate and source, and the output ac voltage is taken between drain and source. Thus the source electrode of this triode device is common to input and output, hence the designation of this JFET configuration as a CS amplifier. A good choice of the dc operating point or quiescent point (Q point) for an amplifier is in the middle of the active region at IDS = IDSS /2. This allows for the maximum symmetrical drain current swing, from the quiescent level of IDSQ = IDSS /2, down to a minimum of IDS @ 0, and up to a maximum of IDS = IDSS . This choice for the Q point is also a good one from the standpoint of allowing for an adequate safety margin for the location FIGURE 24.12 Effect of forward bias on VGS. g dI dV I V V V m DS GS DSS GS P P = = - Ê Ë Á ˆ ¯ ˜ - 2 1 1 - Ê Ë Á ˆ ¯ ˜ = V V I I GS P DS DSS g I I I V I I V m DSS DS DSS P DS DSS P = - = × - 2 2 / FIGURE 24.13 Common-source amplifier
FIGURE 24.14 Transfer characteristi of the actual Q point due to the inevitable variations in device and component characteristics and values. This safety margin should keep the Q point well away from the extreme limits of the active region, and thus ensure operation of the JFET in the active region under most conditions. If Ipss =+10 mA, then a good choice for the Q point would thus be around +5.0 mA. If Vp=-4 V, then 2√5mA·10mA 3.54mA/V=3.54mS If a small ac signal voltage vas is superimposed on the dc gate bias voltage VGs, only a small segment of the transfer characteristic adjacent to the Q point will be traversed, as shown in Fig. 24.14. This small segment will be close to a straight line, and as a result the ac drain current ids will have a waveform close to that of the ac voltage applied to the gate. The ratio of in, to vGs will be the slope of the transfer curve as given by ia, / vgs dps/dvgs=8m. Thus ia,= 8mVGs If the net load driven by the drain of the JFET is the drain load resistor R, as shown in Fig. 24.13, then the ac drain current ids will produce an ac drain voltage of vas =-ids Rp Sin ids=8m,VGs, this becomes vas=-8m vs. Rp. The ac small-signal voltage gain from gate to drain thus becomes Av=vo/vin=vas /vs=-8mt Rp. The negative sign indicates signal inversion as is the case for a CS amplifier. If the dc drain supply voltage is VDp=+20 V, a quiescent drain-to-source voltage of Vpso= Vpp/2=+10 V will result in the JFET being biased in the middle of the active region. Since Inso =+5 mA in the example under consideration, the voltage drop across the drain load resistor Rp is 10 V. Thus Rp= 10 V/5 mA=2 kQ2. The ac mall-signal voltage gain Ay thus becomes Ay =-8mRp=-354 mS 2 kQ2=-707 Note that the voltage gain is relatively modest as compared to the much larger voltage gains that can be obtained in a bipolar-junction transistor(BJT) common-emitter amplifier. This is due to the lower transfer conductance of both JFETs and MOSFETs(metal-oxide semiconductor field-effect transistors) as compared to BJTs. For a BJT the transfer conductance is given by gm =Ic/Vr, where Ic is the quiescent collector current and Vr=klq= 25 mV is the thermal voltage. At Ic=5 mA, 8m=5 mA/25 mV=200 mS, as compared to only 3.5 mS for the JFET in this mple. With a net load of 2 kQ2, the BJT voltage gain will be -400 as compared to the JFET voltage gain of only 7. 1. Thus FETs do have the disadvantage of a much lower transfer conductance, and therefore vol gain, than BJTs operating under similar quiescent current levels, but they do have the major advantage much higher input impedance and a much lower input current. In the case of a ]FET the input signal is applied to the reverse-biased gate-to-channel pn junction and thus sees a very high impedance In the case of a common- emitter B]T amplifier, the input signal is applied to the forward-biased base-emitter junction, and the input impedance is given approximately by in =BE=1.5.B. V/Ic If Ic=5 mA and p=200, for example, then Ii=1500 Q2. This moderate input resistance value of 1.5 kQ2 is certainly no problem if the signal source resistance is less than around 100 Q2. However, if the source resistance is above 1 kQ, then there will be a substantial signal loss in the coupling of the signal from the signal source to the base of the transistor. If the source resistance is in the range of above 100 kQ, and certainly if it is above 1 MQ, then there will be severe signal attenuation lue to the BJT input impedance, and the FET amplifier will probably offer a greater overall voltage gain. Indeed, when high-impedance signal sources are encountered, a multistage amplifier with a FET input stage followed by cascaded B]T stages is often used c 2000 by CRC Press LLC
© 2000 by CRC Press LLC of the actual Q point due to the inevitable variations in device and component characteristics and values. This safety margin should keep the Q point well away from the extreme limits of the active region, and thus ensure operation of the JFET in the active region under most conditions. If IDSS = +10 mA, then a good choice for the Q point would thus be around +5.0 mA. If VP = –4 V, then If a small ac signal voltage vGS is superimposed on the dc gate bias voltage VGS , only a small segment of the transfer characteristic adjacent to the Q point will be traversed, as shown in Fig. 24.14. This small segment will be close to a straight line, and as a result the ac drain current ids will have a waveform close to that of the ac voltage applied to the gate. The ratio of ids to vGS will be the slope of the transfer curve as given by id s/vGS @ dID S /dVGS = gm . Thus ids @ gm vGS . If the net load driven by the drain of the JFET is the drain load resistor R D, as shown in Fig. 24.13, then the ac drain current ids will produce an ac drain voltage of vds = –ids · RD. Since ids = gm vGS , this becomes vds = –gm vGS · R D. The ac small-signal voltage gain from gate to drain thus becomes AV = vO /vin = vd s/vGS = –gm · RD . The negative sign indicates signal inversion as is the case for a CS amplifier. If the dc drain supply voltage is VDD = +20 V, a quiescent drain-to-source voltage of VDSQ = VDD /2 = +10 V will result in the JFET being biased in the middle of the active region. Since IDSQ = +5 mA in the example under consideration, the voltage drop across the drain load resistor RD is 10 V. Thus RD = 10 V/5 mA = 2 kW. The ac small-signal voltage gain AV thus becomes AV = –gm · RD = –3.54 mS · 2 kW = –7.07. Note that the voltage gain is relatively modest as compared to the much larger voltage gains that can be obtained in a bipolar-junction transistor (BJT) common-emitter amplifier. This is due to the lower transfer conductance of both JFETs and MOSFETs (metal-oxide semiconductor field-effect transistors) as compared to BJTs. For a BJT the transfer conductance is given by gm = IC /VT , where IC is the quiescent collector current and VT = kT/q @ 25 mV is the thermal voltage. At IC = 5 mA, gm = 5 mA/25 mV = 200 mS, as compared to only 3.5 mS for the JFET in this example. With a net load of 2 kW, the BJT voltage gain will be –400 as compared to the JFET voltage gain of only 7.1. Thus FETs do have the disadvantage of a much lower transfer conductance, and therefore voltage gain, than BJTs operating under similar quiescent current levels, but they do have the major advantage of a much higher input impedance and a much lower input current. In the case of a JFET the input signal is applied to the reverse-biased gate-to-channel pn junction and thus sees a very high impedance. In the case of a commonemitter BJT amplifier, the input signal is applied to the forward-biased base-emitter junction, and the input impedance is given approximately by rin = rBE @ 1.5 · b · VT /IC. If IC = 5 mA and b = 200, for example, then rin @ 1500 W. This moderate input resistance value of 1.5 kW is certainly no problem if the signal source resistance is less than around 100 W. However, if the source resistance is above 1 kW, then there will be a substantial signal loss in the coupling of the signal from the signal source to the base of the transistor. If the source resistance is in the range of above 100 kW, and certainly if it is above 1 MW, then there will be severe signal attenuation due to the BJT input impedance, and the FET amplifier will probably offer a greater overall voltage gain. Indeed, when high-impedance signal sources are encountered, a multistage amplifier with a FET input stage followed by cascaded BJT stages is often used. FIGURE 24.14 Transfer characteristic. g I I V m DS DSS P = × - = × = = 2 2 5 10 3 54 3 54 mA mA 4 V . . mA/V mS
AVDD RNET CCl 2 RGS RSS FIGURE 24.15 Effect of ras on Rnet FIGURE 24. 16 Active load circuit JFET Output Resistance Dynamic Drain-to-Source Condt For the JFET in the active region the drain current Ips is a strong function of the gate-to-source voltage VGs but is relatively independent of the drain-to-source voltage Vps. The transfer equation has previously been stated as Ins Ioss [1-(vGs/vp))2. The drain current will, however, increase slowly with increasing Vps. To take this dependence of Ips on Vps into account, the transfer equation can be modified to give where VA is a constant called the Early voltage and is a parameter of the transistor with units of volts. The early voltage V is generally in the range of 30 to 300 V for most JFETs. The variation of the drain current with drain voltage is the result of the channel length modulation effect in which the channel length decreases as the drain voltage increases. This decrease in the channel length results in an increase in the drain current. In BJTs a similar effect is the base width modulation effec The dynamic drain-to-source conductance is defined as gas, =dps/dvps and can be obtained from the modified transfer equation Ips=Ioss [1-(VGs/Vp)2[1+ Vps/Va as simply gds=Ios/Va. The reciprocal of &, is dynamic drain-to-source resistance ras, so ras=1/ gds=VA/IDs. If, for example, VA= 100 V, we have that ras =100 V/ID At Ips=1 mA, ras =100 V/l mA= 100 kQ, and at Ips= 10 mA, Tds =10 kQ2 Equivalent Circuit Model of CS Amplifier Stage A small-signal equivalent circuit model of a CS FET amplifier stage is shown in Fig. 24.15. The ac small-signal oltage gain is given by Ay =-8m Rnet where rnet=[rarp rl]is the net load driven by the drain for the ET and includes the dynamic drain-to-source resistance Tas. Since tas, is generally much larger than [RDRil,it will usually be the case that R =[RR, 1, and T, can be neglected. There are, however, some cases in which must be taken into account. This is especially true for the case in which an active load is used, as shown in Fig.24.16.For this case Rnet =[tasllralRi, and Tas can be a limiting factor in determining the voltage gain Consider an example for the active load circuit of Fig. 24.16 for the case of identical JFETs with the same quiescent current. Assume that RL > Tas so that Rnet [ramla]= VA/(2IpsQ). Let Ipso= Ipss/2, so 8m -2 IDss. oso/(Ip)=2/2loso/(Vp). The voltage gain is Vp If VA=100V and Vp=-2 V, we obtain Ay=-70, so we see that with active loads relatively large voltage gains can be obtained with Fets c 2000 by CRC Press LLC
© 2000 by CRC Press LLC JFET Output Resistance Dynamic Drain-to-Source Conductance For the JFET in the active region the drain current IDS is a strong function of the gate-to-source voltage VGS but is relatively independent of the drain-to-source voltage VDS . The transfer equation has previously been stated as IDS = IDSS [1 – (VG S /VP)]2 . The drain current will, however, increase slowly with increasing VDS . To take this dependence of IDS on VDS into account, the transfer equation can be modified to give where VA is a constant called the Early voltage and is a parameter of the transistor with units of volts. The early voltage VA is generally in the range of 30 to 300 V for most JFETs. The variation of the drain current with drain voltage is the result of the channel length modulation effect in which the channel length decreases as the drain voltage increases. This decrease in the channel length results in an increase in the drain current. In BJTs a similar effect is the base width modulation effect. The dynamic drain-to-source conductance is defined as gds = dID S /dVDS and can be obtained from the modified transfer equation IDS = IDSS [1 – (VG S /VP)]2 [1 + VD S /VA] as simply gds = ID S /VA. The reciprocal of gds is dynamic drain-to-source resistance rds , so rds = 1/gds = VA /IDS . If, for example, VA = 100 V, we have that rds = 100 V/IDS . At IDS = 1 mA, rds = 100 V/1 mA = 100 kW, and at IDS = 10 mA, rds = 10 kW. Equivalent Circuit Model of CS Amplifier Stage A small-signal equivalent circuit model of a CS FET amplifier stage is shown in Fig. 24.15. The ac small-signal voltage gain is given by AV = –gm · Rnet , where Rnet = [rds**RD **RL] is the net load driven by the drain for the FET and includes the dynamic drain-to-source resistance rds. Since rds is generally much larger than [RD**RL], it will usually be the case that Rnet @ [RD**RL], and rds can be neglected. There are, however, some cases in which rds must be taken into account. This is especially true for the case in which an active load is used, as shown in Fig. 24.16. For this case Rnet = [rds1**rds2**RL], and rds can be a limiting factor in determining the voltage gain. Consider an example for the active load circuit of Fig. 24.16 for the case of identical JFETs with the same quiescent current. Assume that RL >> rds so that Rnet @ [rds1**rds2] = VA/(2IDSQ). Let IDSQ = IDSS /2, so gm = – . The voltage gain is If VA = 100 V and VP = –2 V, we obtain AV = –70, so we see that with active loads relatively large voltage gains can be obtained with FETs. FIGURE 24.15 Effect of rds on Rnet. FIGURE 24.16 Active load circuit. I I V V V V DS DSS GS P DS A = - Ê Ë Á ˆ ¯ ˜ + Ê Ë Á ˆ ¯ ˜ 1 1 2 2 IDSS × IDSQ –VP § ( ) 2 2IDSQ –VP = § ( ) A g R I V V I V V V m DSQ P A DSQ A P = - × net = ¥ = 2 2 2 2