Single-cycle vs. Multi-cycle: Control & Data. Single-cycle machine:- Control signals are generated in the same clock cycle as datasignals are operated on- Everything related to an instruction happens in one clockcycle. Multi-cycle machine:- Control signals needed inthe next cycle can be generated inthe previous cycle- Latency of control processing can be overlapped with latencyof datapath operation: We will see the difference clearly in microprogrammedmulti-cycle microarchitectureComputerArchitecture11
Computer Architecture Single-cycle vs. Multi-cycle: Control & Data • Single-cycle machine: – Control signals are generated in the same clock cycle as data signals are operated on – Everything related to an instruction happens in one clock cycle • Multi-cycle machine: – Control signals needed in the next cycle can be generated in the previous cycle – Latency of control processing can be overlapped with latency of datapath operation • We will see the difference clearly in microprogrammed multi-cycle microarchitecture 11
Many Ways of Datapath and Control DesignThere are many ways of designing the data path andcontrol logic: Single-cycle, multi-cycle, pipelined datapath and control? Single-bus vs. multi-bus datapaths:Hardwired/combinational vs.microcoded/microprogrammedcontrol-Control signalsgeneratedbycombinational logicversus- Control signals stored in a memory structureControl signals and structure depend on the datapathdesignComputerArchitecture12
Computer Architecture Many Ways of Datapath and Control Design • There are many ways of designing the data path and control logic • Single-cycle, multi-cycle, pipelined datapath and control • Single-bus vs. multi-bus datapaths • Hardwired/combinational vs. microcoded/microprogrammed control – Control signals generated by combinational logic versus – Control signals stored in a memory structure • Control signals and structure depend on the datapath design 12
Performance Analysis. Execution time of an instruction- {CPI} x {clock cycle time}: Execution time of a program- Sum over all instructions[CPI} x (clock cycle time}]]- {# of instructions} × {Average CPI} x {clock cycle time}: Single cycle microarchitecture performance- CPI = 1- Clock cycle time = long: Multi-cycle microarchitecture performance-CPI=differentforeachinstruction: Average CPI → hopefully smallNow, we havetwodegreesoffreedom- Clock cycle time = shorttooptimize independentlyComputerArchitecture13
Computer Architecture Performance Analysis • Execution time of an instruction – {CPI} x {clock cycle time} • Execution time of a program – Sum over all instructions [{CPI} x {clock cycle time}] – {# of instructions} x {Average CPI} x {clock cycle time} • Single cycle microarchitecture performance – CPI = 1 – Clock cycle time = long • Multi-cycle microarchitecture performance – CPI = different for each instruction • Average CPI à hopefully small – Clock cycle time = short 13 Pqy."yg"jcxg"" vyq"fgitggu"qh"htggfqm vq"qrvkmk|g"kpfgrgpfgpvn{
A Single Cycle Microarchitecture: Single-cycle machineNextASequentialCombinationalLogicLogic(State)ComputerArchitecture14
Computer Architecture A Single Cycle Microarchitecture • Single-cycle machine 14 ANext A Sequen+al Logic (State) Combina+onal Logic
Let's Start with the State Elements.Data and control inputs5Readregister1Readdata 15Readregister2RegistersDWriteregisterReaddata2WritedataRegWriteMemWriteInstructionaddressAddressReaddataInstructionDataWriteInstructiondatamemorymemoryMemReadComputerArchitecture15
Computer Architecture Let’s Start with the State Elements • Data and control inputs 15 PC Instruction memory Instruction address Instruction a. Instruction memory b. Program counter Add Sum c. Adder PC Instruction memory Instruction address Instruction a. Instruction memory b. Program counter Add Sum c. Adder 16 32 Sign extend b. Sign-extension unit MemRead MemWrite Data memory Write data Read data a. Data memory unit Address ALU control RegWrite Registers Write register Read data 1 Read data 2 Read register 1 Read register 2 Write data ALU result ALU Data Data Register numbers a. Registers b. ALU Zero 5 5 5 3