Remember: Programmer Visible (Architectural) StateM[0]M[1]M[2]M[3]RegistersM[4]givenspecialnames intheISA(as opposed to addresses)generalvs.specialpurposeM[N-1]ProgramCounterMemoryarrayofstoragelocationsmemoryaddressindexedbyanaddressofthecurrentinstructionInstructions (and programs) specify how to transformthevaluesof programmervisible stateComputerArchitecture
Computer Architecture Remember: Programmer Visible (Architectural) State 6 M[0] M[1] M[2] M[3] M[4] M[N-1] Memory array of storage loca+ons indexed by an address Program Counter memory address of the current instruc+on Registers - given special names in the ISA (as opposed to addresses) - general vs. special purpose Instruc+ons (and programs) specify how to transform the values of programmer visible state
Single-cycle vs. Multi-cycle Machines: Single-cycle machinesEachinstructiontakesasingleclockcycle-All stateupdates madeat the end of an instruction's execution- Big disadvantage: The slowest instruction determines cycle time → longclock cycle timeMulti-cyclemachines-Instructionprocessingbroken intomultiplecycles/stages- State updates can be made during an instruction's execution- Architectural state updates made only at the end of an instruction'sexecution- Advantage over single-cycle: The slowest "stage" determines cycle timeBoth single-cycleand multi-cycle machines literallyfollowthevonNeumannmodelatthemicroarchitecturelevelComputerArchitecture
Computer Architecture Single-cycle vs. Multi-cycle Machines • Single-cycle machines – Each instruction takes a single clock cycle – All state updates made at the end of an instruction’s execution – Big disadvantage: The slowest instruction determines cycle time à long clock cycle time • Multi-cycle machines – Instruction processing broken into multiple cycles/stages – State updates can be made during an instruction’s execution – Architectural state updates made only at the end of an instruction’s execution – Advantage over single-cycle: The slowest “stage” determines cycle time n Both single-cycle and multi-cycle machines literally follow the von Neumann model at the microarchitecture level 7
Instruction Processing“Cycle"Instructions are processed under the direction of a"controlunit" step by step.Instruction cycle: Sequence of steps to process an instructionFundamentally,thereare sixphases:FetchDecodeEvaluate AddressFetch OperandsExecuteStore ResultNot all instructions require all six stagesComputerArchitecture
Computer Architecture Instruction Processing “Cycle” • Instructions are processed under the direction of a “control unit” step by step. • Instruction cycle: Sequence of steps to process an instruction • Fundamentally, there are six phases: • Fetch • Decode • Evaluate Address • Fetch Operands • Execute • Store Result • Not all instructions require all six stages 8
Instruction Processing“Cycle"vs.Machine Clock Cycle: Single-cycle machine:- All six phases of the instruction processing cycle take asingle machine clock cycle to completeMulti-cycle machine:- All six phases of the instruction processing cycle cantake multiple machine clock cycles to complete- In fact, each phase can take multiple clock cycles tocompleteComputerArchitecture
Computer Architecture Instruction Processing “Cycle” vs. Machine Clock Cycle • Single-cycle machine: – All six phases of the instruction processing cycle take a single machine clock cycle to complete • Multi-cycle machine: – All six phases of the instruction processing cycle can take multiple machine clock cycles to complete – In fact, each phase can take multiple clock cycles to complete 9
Instruction Processing Viewed Another WayInstructions transform Data (A) to Data' (A')This transformation is done by functional unitsUnitsthat"operate"ondataThese units need to be told what to do to the data: An instruction processing engine consists of twocomponents- Datapath: Consists of hardware elements that deal with andtransformdatasignalsfunctionalunitsthatoperateondatahardware structures (e.g.wires and muxes)that enablethe flow ofdata intothefunctional unitsand registersstorage units that store data (e.g., registers)- Control logic: Consists of hardware elements that determinecontrolsignals,i.e.signalsthatspecifywhatthedatapathelementsshoulddotothedataComputerArchitecture10
Computer Architecture Instruction Processing Viewed Another Way • Instructions transform Data (A) to Data’ (A’) • This transformation is done by functional units – Units that “operate” on data • These units need to be told what to do to the data • An instruction processing engine consists of two components – Datapath: Consists of hardware elements that deal with and transform data signals • functional units that operate on data • hardware structures (e.g. wires and muxes) that enable the flow of data into the functional units and registers • storage units that store data (e.g., registers) – Control logic: Consists of hardware elements that determine control signals, i.e., signals that specify what the datapath elements should do to the data 10