For Now,We Will Assume. "Magic" memory and register file. Combinational read- output of the read data port is a combinational function of theregister file contents and the corresponding read select port: Synchronous writethe selected register is updated on the positive edge clocktransitionwhen writeenableisasserted.Cannot affect read outputinbetweenclockedges: Can affect read output at clock edges (but who cares?): Single-cycle, synchronous memory-- Contrast this with memory that tells when the data is ready- i.e., Ready bit: indicating the read or write is doneComputerArchitecture16
Computer Architecture For Now, We Will Assume • “Magic” memory and register file • Combinational read – output of the read data port is a combinational function of the register file contents and the corresponding read select port • Synchronous write – the selected register is updated on the positive edge clock transition when write enable is asserted • Cannot affect read output in between clock edges • Can affect read output at clock edges (but who cares?) • Single-cycle, synchronous memory – Contrast this with memory that tells when the data is ready – i.e., Ready bit: indicating the read or write is done 16
Instruction Processing: 5 generic steps- Instruction fetch (IF)Instruction decodeand register operand fetch (ID/RF) Execute/Evaluate memory address (EX/AG)- Memory operand fetch (MEM) Store/writeback result (WB)WBDataIFRegister#PCAddressRegistersAddressInstructionAister#InstructionID/RFDatamemoryEX/AGRegister#memoryDataMEMComputerArchitecture17
Computer Architecture Instruction Processing • 5 generic steps – Instruction fetch (IF) – Instruction decode and register operand fetch (ID/RF) – Execute/Evaluate memory address (EX/AG) – Memory operand fetch (MEM) – Store/writeback result (WB) 17 Registers Register # Data Register # Data memory Address Data Register # PC Instruction ALU Instruction memory Address IF ID/RF EX/AG MEM WB
What Is To Come: The Full DatapathPCSrc=JumpJump address [310]Instruction [250] Shiflef22628PC+4 [3128]ALUAddresultRegDstPCSrc,=BrTakeneft2JumpBranchMemReadInstruction [3126]MemtoRegControlALUOPMemWriteALUSrCRegWriteInstruction [2521]ReadReadregister1ReadaddressInstruction [2016]data 1Readregister2bcondInstructionALUALURegisters Read[310]ReadWriteMdata 2AddressresultdataInstructionregisterumemoryInstruction [15-11]WriteDatadatamemoryWritedata1632Instruction [150]SignALUoperationextendALUontreInstruction [5- 0]JAL,JR,JALRomittedComputerArchitecture18
Computer Architecture What Is To Come: The Full Datapath 18 Shift left 2 PC Instruction memory Read address Instruction [31– 0] Data memory Read data Write data Registers Write register Write data Read data 1 Read data 2 Read register 1 Read register 2 Instruction [15– 11] Instruction [20– 16] Instruction [25– 21] Add ALU result Zero Instruction [5– 0] MemtoReg ALUOp MemWrite RegWrite MemRead Branch Jump RegDst ALUSrc Instruction [31– 26] 4 M u x Instruction [25– 0] Jump address [31– 0] PC+4 [31– 28] Sign extend 16 32 Instruction [15– 0] 1 M u x 1 0 M u x 0 1 M u x 0 1 ALU control Control Add ALU result M u x 0 1 0 ALU Shift left 2 26 28 Address PCSrc2=Br Taken PCSrc1=Jump ALU opera+on bcond JAL, JR, JALR omi\ed
Single-Cycle Datapath forArithmetic and Logical InstructionsComputerArchitecture19
Computer Architecture Single-Cycle Datapath for Arithmetic and Logical Instructions 19
R-Type ALU InstructionsAssembly (e.g., register-register signed addition)ADD rdreg rSreg rtregMachine encoding00rtrdADDR-typers6-bit5-bit5-bit5-bit5-bit6-bitSemanticsif MEM[PCl == ADD rd rs rtGPR[rd] GPR[rs] + GPR[rt]PC PC + 4ComputerArchitecture20
Computer Architecture R-Type ALU Instructions • Assembly (e.g., register-register signed addition) ADD rdreg rsreg rtreg • Machine encoding • Semantics if MEM[PC] == ADD rd rs rt GPR[rd] ← GPR[rs] + GPR[rt] PC ← PC + 4 20 0 6-bit rs 5-bit rt 5-bit rd R-type 5-bit 0 5-bit ADD 6-bit