TEXTIO Signal clk: bity Signal din bit-vector(7 down to OB Variable li liney File infflestext is in“ datain” Readline(infile,B Read(ck)读入了1位 Read(ldin):←一读入了8位 100001010 01101100 110110011 由行变量读入数据变量的数据由数 据变量的属性决定 c din
•TEXTIO Signal clk : bit; Signal din : bit_vector (7 down to 0); Variable li : line; File infile:text is in “data.in”; Readline (infile,li); Read (li,clk); Read (li,din); 1 0 0 0 0 1 0 1 0 0 1 1 0 1 1 0 0 1 1 1 0 1 1 0 0 1 1 . . . clk din 由行变量读入数据变量的数据由数 据变量的属性决定 读入了1位 读入了8位
TEXTIO 5)写一行到输出文件 RITELINE(文件变量,行变量); 6)写一个数据至行 vRE(行变量,数据变量,起始位置,字符数) LEFT/RIGHT
•TEXTIO 5）写一行到输出文件 WRITELINE（文件变量，行变量）； 6）写一个数据至行 WRITE（行变量，数据变量，起始位置，字符数）； LEFT/RIGHT
TEXTIO-write LIBRARY ieee; use ieee std_logic_1164.allp use ieee std_logic_textio.all; library std; use std textio.all entity textiot is port(din in std_logic_vector( 3 downto O)F r,C,h, elkin std_logic) end textioth
•TEXTIO--write LIBRARY ieee; use ieee.std_logic_1164.all; use ieee.std_logic_textio.all; library std; use std.textio.all; entity textiot is port(din : in std_logic_vector(3 downto 0); r,c,h,clk:in std_logic); end textiot;
architecture beh of textiot is file outhtext is out filleout begin process(clk) variable lInNEy variable iNteger; begin if(clk'event and clke"then write(lin, h, left, 1)E write(in, G, left, 1)B write(in,lefty 1B write(in, din, right, 4; writeline(outf, lin; end if; end process; end behs
architecture beh of textiot is file outf:text is out "fileout"; begin process(clk) variable lin:line; variable k:integer; begin if(clk'event and clk='1')then write(lin,h,left,1); write(lin,c,left,1); write(lin,r,left,1); write(lin,din,right,4); writeline(outf,lin); end if; end process; end beh;
TEXTIO-write ame ue 10,12·+·3,1:0,1,,15310 210,+,0,1,的,1 Dd in b din(3) D din(2) b din(1) :0 D- c Dh …i0…i D clk
•TEXTIO--write