Lo0P·F0R循环 [标号]: FoR循环变量IN离散范围LooP 顺序处理语句; END LOOP[标号] 例 ASUM: FoR k IN 1 To 9 Loop sum=k+sum; END LOOP ASUM:
LOOP•FOR循环 [标号]： FOR 循环变量 IN 离散范围 LOOP 顺序处理语句； END LOOP [标号]； 例： ASUM: FOR k IN 1 TO 9 Loop sum=k+sum; END LOOP ASUM;
LAB 4-bit Left shifter FOR LOOP using a Variable shft Ift d out 76543210 Id in
LAB 4-bit Left Shifter FOR LOOP using a Variable d_out d_in shft_lft 7 6 5 4 3 2 1 0
LIBRARY eeep USE ieee std_logic_1164allF ENTITY Shifts PORT( shft_Ift in std_logic d_in in std_logic_vector (3 downto O)B g_out out std_logic_vector(7 downto ODE END Shifteh
LIBRARY ieee; USE ieee.std_logic_1164.all; ENTITY shift4 IS PORT ( shft_lft : in std_logic; d_in : in std_logic_vector(3 downto 0); q_out : out std_logic_vector(7 downto 0)); END shift4; - - to be continue
ARCHITECTURE logic OF shift4 Is BEGIN Variable Declaration PROCESS (d_in, shft_Ift) VARIABLE shft_var std_logic_vector (7 DOWNTO VARIABLE HHo Variable is initialized BEGIN shft_var(7 downto 4):=0000i shft_var(3 downto O)H ding
ARCHITECTURE logic OF shift4 IS BEGIN PROCESS (d_in, shft_lft) VARIABLE shft_var : std_logic_vector (7 DOWNTO 0); VARIABLE i:positive; BEGIN shft_var(7 downto 4) := "0000"; shft_var(3 downto 0) := d_in; - - to be continue Variable Declaration Variable is initialized
Enables shift-left F shft lift〓"THEN FORINT DOWNTO 4 LOG Shifts left by 4 shft_var( : shft_var(-4/E END LOOP shft_var(3 downto O)H “0000 ELSE Fills the LsBs with zeros shft_var :E shft_var;No shifting END F a_out <e shft va Variable is assigned to a Signal before the end of the Process to END PROCESSE synthesize to a piece of hardware END logic
IF shft_lft = '1' THEN FOR i IN 7 DOWNTO 4 LOOP shft_var(i) := shft_var(i-4); END LOOP; shft_var(3 downto 0) := “0000 ” ; ELSE shft_var := shft_var; END IF; q_out <= shft_var; END PROCESS; END logic; Enables shift-left Shifts left by 4 Fills the LSBs with zeros No shifting Variable is assigned to a Signal before the end of the Process to synthesize to a piece of hardware