An introduction to IC testing Far from being an adjunct to the production of integrated circuits,stage-by-stage testing represents a vital,and highly complex,part of the manufacturing process Frederick Van Veen Teradyne,Inc. IC testing has evolved from the patterns established years into the past for the origins of the patterns that some years ago in the production of semiconductors. have unfolded. Since manual testing cannot meet the complex needs The first automatic semiconductor test equipment to be indigenous to IC manufacture,highly sophisticated marketed commercially was manually programmed to instruments and test systems have developed that supply the proper biases,limits,and classification cri- are automatically programmed by computer,tape,or terions.Once programmed,the instruments were fully printed-circuit card.This article focuses on many of automatic in operation,the chief restriction on test rate the problems encountered and techniques employed, being the speed with which an operator could insert and also the requirements imposed on automatic IC transistors or diodes into the test socket and place them in testing systems. bins according to test results.Automatic handling equip- ment was soon introduced to perform both of these func- tions,and multiplexers were developed to give the test equipment even greater leverage. More than 300 million monolithic integrated circuits The manually programmed semiconductor tester sur- will have been sold in the United States during 1971,and vives in the form of instruments used for the incoming a conservative guess on industry-wide yield would lead inspection and evaluation of transistors,diodes,and,to a one to think that well over a billion chips were tested in very limited degree,ICs.It represents a practical approach order to produce these 300 million marketable ICs. to the problem of testing relatively small quantities of Each good circuit,in the course of its travel from wafer to devices,each of which requires a relatively small number end use,is probably tested an average of three times,and of tests.Most IC testing,however,involves complexity each test involves the qualification of many circuit func- beyond the practical limitations of manual programming. tions and parameters. This situation has led to the development of the test Without carrying this exercise to extremes,it is obvious equipment on which most attention is focused these that the integrated circuit has brought with it a tidal days-instruments and test systems automatically pro- wave of testing.Or,to turn the picture around,the intro- grammed by computer,tape,or printed-circuit card. duction of automatic equipment capable of making tens The computer,of course,offers not only test-plan storage of thousands of tests on a device in a few seconds has but also the important ability to base the conditions of made the integrated circuit commercially viable. one test on the results of a previous test.The computer Because IC testing is in the mainstream of the produc- (and in particular the minicomputer)has become a major tion process,it is very much in the mainstream of the element in the IC testing picture,and it is typical of our chronic IC cost/price competition.For this reason the bootstrap technology that the minicomputer is in a very technology of IC testing is always colored by economic real sense a product of its own making. considerations.It is usually far more important to Figure 1 is a generalized clock diagram of a com- accommodate another multiplexed test station than it is puter-controlled Ic test system,as represented by a to add another digit of resolution. number of commercial equipments.The test program is loaded into the computer via paper or magnetic tape Evolution or by punched cards.Instructions from the computer IC testing is,of course,only a logical extension of are sent to an interface or control unit,which passes transistor and diode testing,so we must look about ten them along to the appropriate elements of the system. 28 IEEE spectrum DECEMBER 1971
An introduction to IC testing Far from being an adjunct to the production of integrated circuits, stage-by-stage testing represents a vital, and highly complex, part of the manufacturing process Frederick Van Veen Teradyne, Inc. IC testing has evolved from the patterns established years into the past for the origins of the patterns that some years ago in the production of semiconductors. have unfolded. Since manual testing cannot meet the complex needs The first automatic semiconductor test equipment to be indigenous to IC manufacture, highly sophisticated marketed commercially was manually programmed to instruments and test systems have developed that supply the proper biases, limits, and classification criare automatically programmed by computer, tape, or terions. Once programmed, the instruments were fully printed-circuit card. This article focuses on many of automatic in operation, the chief restriction on test rate the problems encountered and techniques employed, being the speed with which an operator could insert and also the requirements imposed on automatic IC transistors or diodes into the test socket and place them in testing systems. bins according to test results. Automatic handLing equipment was soon introduced to perform both of these functions, and multiplexers were developed to give the test equipment even greater leverage. More than 300 million monolithic integrated circuits The manually programmed semiconductor tester surwill have been sold in the United States during 1971, and vives in the form of instruments used for the incoming a conservative guess on industry-wide yield would lead inspection and evaluation of transistors, diodes, and, to a one to think that well over a billion chips were tested in very limited degree, ICs. It represents a practical approach order to produce these 300 million marketable ICs. to the problem of testing relatively small quantities of Each good circuit, in the course of its travel from wafer to devices, each of which requires a relatively small number end use, is probably tested an average of three times, and of tests. Most IC testing, however, involves complexity each test involves the qualification of many circuit func- beyond the practical limitations of manual programming. tions and parameters. This situation has led to the development of the test Without carrying this exercise to extremes, it is obvious equipment on which most attention is focused these that the integrated circuit has brought with it a tidal days-instruments and test systems automatically prowave of testing. Or, to turn the picture around, the intro- grammed by computer, tape, or printed-circuit card. duction of automatic equipment capable of making tens The computer, of course, offers not only test-plan storage of thousands of tests on a device in a few seconds has but also the important ability to base the conditions of made the integrated circuit commercially viable. one test on the results of a previous test. The computer Because IC testing is in the mainstream of the produc- (and in particular the minicomputer) has become a major tion process, it is very much in the mainstream of the element in the IC testing picture, and it is typical of our chronic IC cost/price competition. For this reason the bootstrap technology that the minicomputer is in a very technology of IC testing is always colored by economic real sense a product of its own making. considerations. It is usually far more important to Figure 1 is a generalized clock diagram of a comaccommodate another multiplexed test station than it is puter-controlled IC test system, as represented by a to add another digit of resolution. number of commercial equipments. The test program is loaded into the computer via paper or magnetic tape Evolution or by punched cards. Instructions from the computer IC testing is, of course, only a logical exten.sion of are sent to an interface or control unlit, which passes transistor and diode testing, so we must look about ten them along to the appropriate elements of the system. 28 IEEE spectrum DECEMBER 1971
Tape or cards Test statlor Computer Control Buffer D/A Multiplexe Test unit converter station Test station FIGURE 1.Basic con- Operator A/D figuration of a com- keyboard Buffer converte puter-controlled IC test system. IC under test FIGURE 2.Block dia- gram of comparison- type functional tester. Pattern generator Reject Exclusive OR lamp Π几u Instructions to apply stimuli to the IC are buffered, application among producers and high-volume users of converted into analog voltages,and delivered to the ICs.At the other end of the scale is the comparison-type pins at the test sockets of multiplexed test stations (or to tester,shown in block-diagram form in Fig.2.Here a wafer probers),which are time-shared under computer binary or random pattern is applied to the device under control.The output functions of the IC are converted test and at the same time to a reference unit having the into digital form,buffered,and returned to the control same truth table as the unknown.The outputs are com- unit and computer for processing.The operator exercises pared and a reject lamp lights when they differ.Instru- overall control of the system by teletypewriter keyboard ments using this technique are relatively inexpensive and commands. are preferred for incoming inspection of ICs in low or Systems of the type shown in Fig.1 typically cost moderate volume. from S50 000 to well over $100 000 and find greatest In some applications,especially those in which in- Van Veen-An introduction to IC testing 29
FIGURE 1. Basic configuration of a computer-controlled IC test system. IC under test FIGURE 2. Block diagram of comparisontype functional tester. Pattern r Il*l * e r l l | | ~~~~~~~~~~~Exclusive OR Rlamrnpt Reference Instructions to apply stimuli to the IC are buffered, application among producers and high-volume users of converted into analog voltages, and delivered to the ICs. At the other end of the scale is the comparison-type pins at the test sockets of multiplexed test stations (or to tester, shown in block-diagram form in Fig. 2. Here a wafer probers), which are time-shared under computer binary or random pattern is applied to the device under control. The output functions of the IC are converted test and at the same time to a reference unit having the into digital form, buffered, and returned to the control same truth table as the unknown. The outputs are comunit and computer for processing. The operator exercises pared and a reject lamp lights when they differ. Instruoverall control of the system by teletypewriter keyboard ments using this technique are relatively inexpensive and commands. are preferred for incoming inspection of ICs in low or Systems of the type shown in Fig. 1 typically cost moderate volume. from $50 000 to well over $100 000 and find greatest In some applications, especially those in which inVan Veen-An introduction to IC testing 29
Driver/comparator module (1 per channel) Voltage reterence Current-limit hg reference Parametric Voltage measurement reference A system Current-limit Kelvin reterence Drivers Voltage reference Current-limit Parametric reterence Voltage system reference Kelvin Current-limit reference High limit High/iow logic Sold state Low limit Reed relay Relevance Voltage Comparators nth result 0n+4 0n+3 on+2 Transterred unde 0n+1 sottware contro! o nth channel FIGURE 3.Driver/comparator t switching,as employed in the Teradyne J283 computer-opera- ted Ic test system. coming inspection is included,the ideal system or instru- Clock-rate testing,which refers to the functional ment would be versatile enough to handle bipolar and testing of MOS digital circuits at their maximum and metal oxide semiconductor (MOS)devices,both digital minimum repetition rates. and linear.Although such"universal"systems have been Parametric testing,which measures IC voltages and attempted,they are usually hybridizations of individual currents at high accuracy and a relatively low test rate. special-purpose test systems,based on the sharing of Direct-current parametric testing refers to tests in which certain common elements (e.g.,the controlling com- the inputs are maintained until the outputs reach a stable puter). state.Pulse parametric (or dynamic)testing refers to For all practical purposes,however,the testing of tests of the time-related properties of an IC. bipolar,MOS,and linear ICs can be considered three To summarize,the two chief classes of digital-IC distinct subjects.The technologies are different.and the testing are functional (high rate,low accuracy)and three types of devices represent three subindustries,each parametric (low rate,high accuracy).Note that the of which can afford to optimize its production processes. recording of a parametric value is nor essential to para- metric testing. Defining terms After some years of semantic chaos,the lexicon of The testing of digital bipolar ICs IC testing is beginning to stabilize.The principal branches The digital bipolar class represents by far the largest of the tree are as follows: segment of IC production today,and testing techniques Functional testing,which checks the truth table (or are somewhat more standardized than they are for other a subset of it)of a digital IC by applying a sequence of device families.The usual pattern is:functional testing input words at nominal voltage levels and checking to find catastrophic failures caused by improper packag- the corresponding output words.Functional testing ing,bonding,metalization,photolithography,die mount- usually involves a large number of tests and is therefore ing,etc.and dc and pulse parametric testing to uncover performed at the highest machine speed,at the expense of failures due to surface or oxide defects,such as channeling accuracy. pinholes,etc.Although virtually all ICs are tested func- 30 IEEE spectrum DECEMBER 1971
_-_~~~ ~( pe chanversl)eli ___reference z tv Kli Current-limit _ KlT reference Kelvin _V_oHltagehmit S w _ _ E Sobd state ....._refereance - Reed relay Transferred undee n + 1 l|software control _ nth channel _ FIGURE 3. Driver/comparator crier switching, as employed in the _ ___ Teradyne J283 computer-opera- _ ted IC test system. coming inspection is included, the ideal system or instru- Clock-rate testing, which refers to the functional ment would be versatile enough to handle bipolar and testing of MOS digitatl circuits at their maximum and metal oxide semiconductor (MOS) devices, both digital minimum repetition rates. and linear. Although such "universal" systems have been Parametric testing, which measures IC voltages and attempted, they are usually hybridizations of individual currents at high accuracy and a relatively low test rate. special-purpose test systems, based on the sharing of Direct-current parametric testing refers to tests in which certain common elements (e.g., the controlling com- the inputs are maintained until the outputs reach a stable puter). state. Pulse parametric (or dynamic) testing refers to For all practical purposes, however, the testing of tests ofthe time-related properties ofanlIC. bipolar, MOS, and linear ICs can be considered three To summarize, the two chief classes of digital-IC distinct subjects. The technologies are different, and the testing are functional (high rate, low accuracy) and three types of devices represent three subindustries, each parametric (low rate, high accuracy). Note that the of which can afford to optimize its production processes. recording of a parametric value is not essential to parametric testing. Defining terms After some years of semantic chaos, the lexicon of The testing of digital bipolar lCs IC testing is beginning to stabilize. The principal branches The digital bipolar class represents by far the largest ofthe tree are asrfollows: segment of IC production today, and testing techniques Functional testing, which checks the truth table (or are somewhat more standardized than they are for other a subset of it) of a digital IC by applying a sequence of device families. The usual pattern is: functional testing input words at nominal voltage levels and checking to find catastrophic failures caused by improper packagthe corresponding output words. Functional testing ing, bonding, metalization, photolithography, die mountusually involves a large number of tests and is therefore ing, etc.; and dc and pulse parametric testing to uncover performed at the highest machine speed, at the expense of failures due to surface or oxide defects, such as channeling. accuracy. pinholes, etc. Although virtually all ICs are tested funclogicIEEE spectrum DECEMBER t97a
tionally and for de characteristics,pulse parametric or The functional-testing end of a computer-operated IC dynamic testing is performed chiefly on fast transistor- test system is diagrammed in Fig.3.In this system transistor logic (TTL)or emitter-coupled logic (ECL) (Teradyne's J283 "SLOT"system),each pin of the IC devices. under test is connected to a module that contains two It is important to note that these three types of tests- pairs of programmable"drivers"and a pair of compara- functional,dc parametric,and pulse parametric-are tors.The drivers are actually fast solid-state switches related to distinctly different properties of an IC,and that gate power from buffered digital-to-analog (D/A) that a test sequence of one type only,no matter how voltage sources.The voltage levels from these sources thorough,cannot provide adequate device characteriza- are assigned by computer control,and it is the function tion. of the drivers to switch these voltages into the circuit Functional testing.A digital IC responds to a combina- quickly while preserving waveform integrity.All four tion of high and low inputs (I's and 0's)by producing drivers have programmable current limiting to prevent a certain combination of high and low outputs.Func- device damage. tional testing ensures that the combinations are as they The two comparators receive programmable reference should be for the logic in question.For combinatorial voltages from the buffered source for use in determining devices in which there are relatively few inputs,one can whether IC output levels are above or below specified achieve thorough functional testing through the brute- limits.Note that during functional testing each pin is force approach of exercising all input combinations. always connected to both the driver and detector sec- This approach breaks down,however,when the IC tions of the module,and that only a software command under test contains sequential logic,where the outputs is needed to change a given channel from an input to an are a function not only of the input combination but output or vice versa,an important consideration in the also of the order in which the various inputs are ex- testing of certain ICs having pins that serve both func- ercised. tions.This arrangement also makes it possible for the The presence of sequential logic raises the number of system to apply a programmable load to an output pin possible input combinations and sequences far beyond during testing. the practical reach of even the fastest testers,and the The output of either comparator is observed or not testing problem then becomes one of choosing the best of depending on the presence or absence of a "relevance" the available compromises. software command.Thus,where one wishes to exercise One compromise approach is based on the application an IC but ignore the logic outputs (as,for example,when of random patterns to the inputs and the statistical prob- preconditioning an IC),the comparator output is simply ability that these will test the device adequately.The made nonrelevant.Where it is relevant,the system may shortcomings of this approach are that (1)the chances of be programmed to look for failures in any of three ways testing for every possible failure mode are extremely re- It can look at each pin ("nth result"),sending pass-fail mote,(2)a random pattern makes no allowance for time information back to the computer.Usually,however, delays that flip-flops or other sequential devices may it is not necessary to isolate failures down to pins and it is require at various points in their operation,and (3) sufficient to know that some pin failed at a given point the random pattern does not take into account the neces- in the test sequence.Thus all the nth-result indications sity for "initializing"certain ICs-that is,setting them can be logically oRed to give a "present result."When to some known state before testing can begin. long test patterns are applied even this method (which Alternatively,one can algorithmically generate test requires communication with the computer at each step) patterns designed to detect all the failure modes intrinsic is impractical.In such cases the "present result"indica- to the logic at hand.Software can be developed that tion is automatically strobed into the"cumulative result" will iteratively apply patterns,verify that given failure memory after each logic sentence.The cumulative result modes are or are not detected,and modify the patterns tells the operator that the IC failed somewhere along the accordingly.This is a complex process and one on which line,which is very often the only information that is of much effort is being spent.Commercial pattern-genera- interest. tion services have sprung up in recent years to satisfy the Clock-rate testing.MOS clock-rate testing is ana- growing demand for solutions to the testing problems logous to functional testing,with one important differ- associated with large-scale integration. ence:In bipolar functional testing,the test speed is very In the never-ending search for right combinations of slow compared with the maximum speed at which the IC I's and 0's,it is all too easy to overlook the fact that an will operate,and thus is not a consideration.Clock-rate IC under test sees not 1's and 0's,but fast transitions MOS testing,on the other hand,is conducted near the of voltage or current.These transitions have to be fast maximum frequency of the device,which,for today's enough to simulate the inputs the device will encounter faster devices,is in the region around 5 MHz,with 10 in its end use and to represent decisive changes of state MHz over the not-too-distant horizon.At the other end (i.e.,a transition should not be so slow as to linger in of the spectrum,measurement of the "stay-alive"time the turn-on region of a device),but they should not be so (or minimum operating frequency)of the device may fast as to produce unacceptable overshoot,ringing,or require a test frequency as low as 1 Hz. crosstalk,which can result in double-clocking of devices, Not only must the MOS test system be able to supply channel interference problems,etc.An oscilloscope high-frequency test signals,it also must supply several connected to the test points of a wafer prober will sets of them (phases),each precisely settable with respect speak volumes about an IC test system's ability to test to the others.The number of phases needed depends on ICs reliably.Unless one can take a clean test signal the types of devices to be tested;common requirements for granted,he can never be confident of his test results, are for two or four phases with a phase resolution of 1 ns no matter how elegant the test patterns. or better.The ability to manipulate phases with respect to Van Veen-An introduction to IC testing 31
tionally and for dc characteristics, pulse parametric or The functional-testing end of a computer-operated IC dynamic testing is performed chiefly on fast transistor- test system is diagrammed in Fig. 3. In this system transistor logic (TTL) or emitter-coupled logic (ECL) (Teradyne's J283 "SLOT" system), each pin of the IC devices. under test is connected to a module that contains two It is important to note that these three types of tests- pairs of programmable "drivers" and a pair of comparafunctional, dc parametric, and pulse parametric-are tors. The drivers are actually fast solid-state switches related to distinctly different properties of an IC, and that gate power from buffered digital-to-analog (D/A) that a test sequence of one type only, no matter how voltage sources. The voltage levels from these sources thorough, cannot provide adequate device characteriza- are assigned by computer control, and it is the function tion. of the drivers to switch these voltages into the circuit Functional testing. A digital IC responds to a combina- quickly while preserving waveform integrity. All four tion of high and low inputs (l's and 0's) by producing drivers have programmable current limiting to prevent a certain combination of high and low outputs. Func- device damage. tional testing ensures that the combinations are as they The two comparators receive programmable reference should be for the logic in question. For combinatorial voltages from the buffered source for use in determining devices in which there are relatively few inputs, one can whether IC output levels are above or below specified achieve thorough functional testing through the brute- limits. Note that during functional testing each pin is force approach of exercising all input combinations. always connected to both the driver and detector secThis approach breaks down, however, when the IC tions of the module, and that only a software command under test contains sequential logic, where the outputs is needed to change a given channel from an input to an are a function not only of the input combination but output or vice versa, an important consideration in the also of the order in which the various inputs are ex- testing of certain ICs having pins that serve both funcercised. tions. This arrangement also makes it possible for the The presence of sequential logic raises the number of system to apply a programmable load to an output pin possible input combinations and sequences far beyond during testing. the practical reach of even the fastest testers, and the The output of either comparator is observed or not, testing problem then becomes one of choosing the best of depending on the presence or absence of a "relevance" the available compromises. software command. Thus, where one wishes to exercise One compromise approach is based on the application an IC but ignore the logic outputs (as, for example, when of random patterns to the inputs and the statistical prob- preconditioning an IC), the comparator output is simply ability that these will test the device adequately. The made nonrelevant. Where it is relevant, the system may shortcomings of this approach are that (1) the chances of be programmed to look for failures in any of three ways. testing for every possible failure mode are extremely re- It can look at each pin ("nth result"), sending pass-fail mote, (2) a random pattern makes no allowance for time information back to the computer. Usually, however, delays that flip-flops or other sequential devices may it is not necessary to isolate failures down to pins and it is require at various points in their operation, and (3) sufficient to know that some pin failed at a given point the random pattern does not take into account the neces- in the test sequence. Thus all the nth-result indications sity for "initializing" certain ICs-that is, setting them can be logically oRed to give a "present result." When to some known state before testing can begin. long test patterns are applied even this method (which Alternatively, one can algorithmically generate test requires communication with the computer at each step) patterns designed to detect all the failure modes intrinsic is impractical. In such cases the "present result" indicato the logic at hand. Software can be developed that tion is automatically strobed into the "cumulative result" will iteratively apply patterns, verify that given failure memory after each logic sentence. The cumulative result modes are or are not detected, and modify the patterns tells the operator that the IC failed somewhere along the accordingly. This is a complex process and one on which line, which is very often the only information that is of much effort is being spent. Commercial pattern-genera- interest. tion services have sprung up in recent years to satisfy the Clock-rate testing. MOS clock-rate testing is anagrowing demand for solutions to the testing problems logous to functional testing, with one important differassociated with large-scale integration. ence: In bipolar functional testing, the test speed is very In the never-ending search for right combinations of slow compared with the maximum speed at which the IC l's and 0's, it is all too easy to overlook the fact that an will operate, and thus is not a consideration. Clock-rate IC under test sees not l's and 0's, but fast transitions MOS testing, on the other hand, is conducted near the of voltage or current. These transitions have to be fast maximum frequency of the device, which, for today's enough to simulate the inputs the device will encounter faster devices, is in the region around 5 MHz, with 10 in its end use and to represent decisive changes of state MHz over the not-too-distant horizon. At the other end (i.e., a transition should not be so slow as to linger in of the spectrum, measurement of the "stay-alive" time the turn-on region of a device), but they should not be so (or minimum operating frequency) of the device may fast as to produce unacceptable overshoot, ringing, or require a test frequency as low as 1 Hz. crosstalk, which can result in double-clocking of devices, Not only must the MOS test system be able to supply channel interference problems, etc. An oscilloscope high-frequency test signals, it also must supply several connected to the test points of a wafer prober will sets of them (phases), each precisely settable with respect speak volumes about an IC test system's ability to test to the others. The number of phases needed depends on ICs reliably. Unless one can take a clean test signal the types of devices to be tested; common requirements for granted, he can never be confident of his test results, are for two or four phases with a phase resolution of 1 ns no matter how elegant the test patterns. or better. The ability to manipulate phases with respect to Van Veen-An introduction to IC testing 31
one another adds another dimension to the use of test Whereas functional testing usually involves voltage patterns in LSI testing;an alternative to the use of many swings of 30 volts or less,dc parametric test systems long patterns may be the application of a few worst-case typically can force 100 volts or more.In systems having patterns under varying phase relationships. both functional and parametric test sections,break- Great demands are placed on the drivers of an MOS before-make switching from one to the other is required test system.They must be able to swing 30 volts,at a so that the power available for parametric testing cannot slope of 1 ns/V or better,with minimum overshoot, inadvertently damage the functional-test drivers and ringing,or crosstalk,through cables to automatic hand- comparators. lers or wafer probers.Satisfactory performance results One of the most interesting and significant recent once one recognizes the practical necessity of such cables developments in IC testing has been the growing em- between drivers and the device under test and designs phasis placed on pulse parametric,or dynamic,testing the test system accordingly,using impedance-matching Several factors lie behind this trend.First,speed margins techniques to minimize the effects of cable capacitance. represent the essential differences(and therefore the price Parametric testing.Functional testing,even when premiums)between one device type and another.Second, exhaustively complete,cannot be relied on to determine these differences in operating speed cannot be verified whether an IC will operate in its end use.The test system by dc and functional testing.Third,equipment that can cannot simulate all of the possible circuits in which a reliably measure dynamic performance on a production- device may be used,and it is therefore necessary to line basis has become available only fairly recently measure certain parameters and to compare them against Pulse parametric testing refers to a limited number of specified limits.These measurements will define the time-interval measurements-principally those of propa- fanout capabilities of the device,as well as leakage gation delay,rise time,and fall time.For the fastest current,power dissipation,etc.Usually a few parameters digital devices,these intervals are so short as to challenge are measured for each of a number of input conditions. the state of the measurement art.A test system handling The technique for making dc parametric tests is that ECL and fast TTL logic must be able to measure a of forcing a voltage or current at an input and comparing propagation delay of a nanosecond repeatedly and with the resulting output current or voltage against a limit. a precision of 10 picoseconds. The test result can be taken as a simple go/no-go indica- Some of the key issues in pulse parametric testing have tion,or A/D conversion techniques can be applied to to do with the way parameters are defined and speci- record the actual value of the parameter in question. fied.Rise time,for example,is often defined as the time One such technique is a software-directed sequential it takes a voltage to rise from 10 to 90 percent of its approximation in which a series of go/no-go comparisons maximum value,but,given a pulse with any overshoot is made,the reference converging on the unknown. or ringing,the maximum value and therefore the rise- Since the emphasis in parametric testing is on accuracy, time boundaries are uncertain.A much more rigorous precautions are taken in equipment design to eliminate definition would prescribe actual voltage levels as the stray capacitance and spurious ground currents.Kelvin boundaries for rise and fall times and propagation delay. connections are generally used,in conjunction with The parameters involved in a typical pulse parametric driven guard shields,to minimize cable charging currents test are defined in Fig.4,which illustrates the dynamic that could introduce time-constant delays in circuit characteristics of a typical TTL gate.The rise and fall stabilization. times of the input pulse,t and t,are defined in terms Because a parametric test generally takes much longer of actual voltage levels,not percentages;t and t than a functional test,the interplay between the two are the propagation times from high to low and from low types of test directly affects productivity.The programmer to high levels,respectively,and both are usually specified of a computer-operated system has several options and tested. available to him:He can run all functional tests first, Note that the accuracy with which one can define fpz in order to screen out catastrophic rejects before para and fPLa depends on the accuracy with which the 1.5-volt metric testing;or he may make certain critical parametric thresholds are known,and this in turn is a function of tests first;or he may functionally test,branching into the slope of the voltage transitions (a slow transition a parametric sequence upon failure. rate amplifies any threshold error).Input transition rate should therefore be specified,along with pulse amplitudes and durations Once the characteristics of the input pulse have been FIGURE 4.Dynamic properties of a 5400-series TTL gate specified,the problem becomes one of ensuring that these Pulse parametric system measures rise and fall times characteristics are achieved,not at the output of the and propagation delays tpaL and tpLB. pulse generator but at the test socket.In a self-calibrating system each test pulse is first measured at the test socket tr长 and the pulse generator is automatically adjusted to produce the desired characteristics at the socket. 2.7v 2.7V Early dynamic measurements on ICs were made by 1.5V 1.5V 0.7V 0.7V sampling techniques similar to these well established in high-frequency laboratory measurements.More recently, thet“real-time”ort“single-shot”technique,in which a single time interval is measured in terms of the amount of charge absorbed by a reference capacitor during that time,has achieved widespread acceptance and appears now to predominate. IEEE spectrum DECEMBER 1971
one another adds another dimension to the use of test Whereas functional testing usually involves voltage patterns in LSI testing; an alternative to the use of many swings of 30 volts or less, dc parametric test systems long patterns may be the application of a few worst-case typically can force 100 volts or more. In systems having patterns under varying phase relationships. both functional and parametric test sections, breakGreat demands are placed on the drivers of an MOS before-make switching from one to the other is required test system. They must be able to swing 30 volts, at a so that the power available for parametric testing cannot slope of 1 ns/V or better, with minimum overshoot, inadvertently damage the functional-test drivers and ringing, or crosstalk, through cables to automatic hand- comparators. lers or wafer probers. Satisfactory performance results One of the most interesting and significant recent once one recognizes the practical necessity of such cables developments in IC testing has been the growing embetween drivers and the device under test and designs phasis placed on pulse parametric, or dynamic, testing. the test system accordingly, using impedance-matching Several factors lie behind this trend. First, speed margins techniques to minimize the effects of cable capacitance. represent the essential differences (and therefore the price Parametric testing. Functional testing, even when premiums) between one device type and another. Second, exhaustively complete, cannot be relied on to determine these differences in operating speed cannot be verified whether an IC will operate in its end use. The test system by dc and functional testing. Third, equipment that can cannot simulate all of the possible circuits in which a reliably measure dynamic performance on a productiondevice may be used, and it is therefore necessary to line basis has become available only fairly recently. measure certain parameters and to compare them against Pulse parametric testing refers to a limited number of specified limits. These measurements will define the time-interval measurements-principally those of propafanout capabilities of the device, as well as leakage gation delay, rise time, and fall time. For the fastest current, power dissipation, etc. Usually a few parameters digital devices, these intervals are so short as to challenge are measured for each of a number of input conditions. the state of the measurement art. A test system handling The technique for making dc parametric tests is that ECL and fast TTL logic must be able to measure a of forcing a voltage or current at an input and comparing propagation delay of a nanosecond repeatedly and with the resulting output current or voltage against a limit. a precision of 10 picoseconds. The test result can be taken as a simple go/no-go indica- Some of the key issues in pulse parametric testing have tion, or A/D conversion techniques can be applied to to do with the way parameters are defined and specirecord the actual value of the parameter in question. fied. Rise time, for example, is often defined as the time One such technique is a software-directed sequential it takes a voltage to rise from 10 to 90 percent of its approximation in which a series of go/no-go comparisons maximum value, but, given a pulse with any overshoot is made, the reference converging on the unknown. or ringing, the maximum value and therefore the riseSince the emphasis in parametric testing is on accuracy, time boundaries are uncertain. A much more rigorous precautions are taken in equipment design to eliminate definition would prescribe actual voltage levels as the stray capacitance and spurious ground currents. Kelvin boundaries for rise and fall times and propagation delay. connections are generally used, in conjunction with The parameters involved in a typical pulse parametric driven guard shields, to minimize cable charging currents test are defined in Fig. 4, which illustrates the dynamic that could introduce time-constant delays in circuit characteristics of a typical TTL gate. The rise and fall stabilization. times of the input pulse, tr and tf, are defined in terms Because a parametric test generally takes much longer of actual voltage levels, not percentages; tPHL and tpLH than a functional test, the interplay between the two are the propagation times from high to low and from low types of test directly affects productivity. The programmer to high levels, respectively, and both are usually specified of a computer-operated system has several options and tested. available to him: He can run all functional tests first, Note that the accuracy with which one can define tPHL in order to screen out catastrophic rejects before para- and tPLH depends on the accuracy with which the 1.5-volt metric testing; or he may make certain critical parametric thresholds are known, and this in turn is a function of tests first; or he may functionally test, branching into the slope of the voltage transitions (a slow transition a parametric sequence upon failure. rate amplifies any threshold error). Input transition rate should therefore be specified, along with pulse amplitudes and durations. Once the characteristics of the input pulse have been FIGURE 4. Dynamic properties of a 5400-series TTL gate. specified, the problem becomes one of ensuring that these Pulse parametric system measures rise and fall times characteristics are achieved, not at the outptut of the and propagation delays tpHL and tPLH. pulse generator but at the test socket. In a self-calibrating system each test pulse is first measured at the test socket ~ tr ~ ~ tf ~ and the pulse generator is automatically adjusted to | ~~~~~~~~~~produce ' r ' ' the desired characteristics at the socket. 2.7v 2.7VYv, ~~~~~Early dynamic measurements on ICs were made by <1.5V 1.5 V J~0.7 sampling techniques similar to these well established in itPHL~~~~~~~~high-frequency '< laboratory measurements. More recently, VOH ->I tPLH :E the "real-time' or "singie-shot" technique, in which a Jr - ~~~~~~~~~~~~~single ' | time interval is measured in terms of the amount ,, ,/ ~~~~~~~~of charge absorbed by a reference capacitor during that \ / ~~~~~~~~time, has achieved widespread acceptance and appears ~~~~~~~~now vOL S to predominate. 32 ~~~~~~~~~~~~~~~~~~~~~~~~~~IEEE spectrum DECEMBER 1971