TRANSFER CHARACTER| STICS FOR“soFT” AND HARD DISTORTION IN ADCs OUTPUT INPUT PUT TRANSFER CHARACTERISTICS TRANSFER CHARACTERISTICS Figure 4.10 The actual location of the points of discontinuity depends on the particular data converter architecture, but nevertheless, such discontinuities occur in practically all are relatively unpredictable with respect to input signal level, and therefore sucs ch converters Non-linearity of this type produces high-order distortion products whic specifications as third order intercept point may be less relevant to converters than to amplifiers and mixers For lower-amplitude signals, this constant level hard distortion causes the SFDr of the converter to decrease as input amplitude decreases. The soft distortion in a well-designed converter is only significant for high frequency large-amplitude signals where it may rise above the hard distortion floor required dynamic performance at the required sampling rate and input signal o In a practical system design, the adC is usually selected based primarily on the frequency, using one or more of the above specifications. dc performance may be important also, but is generally of less concern in signal processing applications. Once the ADC is selected, the appropriate interface circuitry must be designed to preserve these levels of ac and dc performance SELECTING THE DRIVE AMPLIFIER BASED ON ADC DYNAMIC PERFORMANCE The adc drive amplifier performs several important functions in a system. First, it isolates the signal source and provides a low-impedance drive to the AdC input. a low-impedance dc and ac drive source is important because the input impedance of the adc may be signal-dependent, and the input may also generate transient load currents during the actual conversion process. A low source impedance at high frequencies minimizes the errors produced by these effects. Second, the drive amplifier provides the necessary gain and level shifting to match the signal to the ADC input voltage range
1 1 TRANSFER CHARACTERISTICS FOR “SOFT” AND “HARD” DISTORTION IN ADCs Figure 4.10 The actual location of the points of discontinuity depends on the particular data converter architecture, but nevertheless, such discontinuities occur in practically all converters. Non-linearity of this type produces high-order distortion products which are relatively unpredictable with respect to input signal level, and therefore such specifications as third order intercept point may be less relevant to converters than to amplifiers and mixers. For lower-amplitude signals, this constant level hard distortion causes the SFDR of the converter to decrease as input amplitude decreases. The soft distortion in a well-designed converter is only significant for high frequency large-amplitude signals where it may rise above the hard distortion floor. In a practical system design, the ADC is usually selected based primarily on the required dynamic performance at the required sampling rate and input signal frequency, using one or more of the above specifications. DC performance may be important also, but is generally of less concern in signal processing applications. Once the ADC is selected, the appropriate interface circuitry must be designed to preserve these levels of ac and dc performance. SELECTING THE DRIVE AMPLIFIER BASED ON ADC DYNAMIC PERFORMANCE The ADC drive amplifier performs several important functions in a system. First, it isolates the signal source and provides a low-impedance drive to the ADC input. A low-impedance dc and ac drive source is important because the input impedance of the ADC may be signal-dependent, and the input may also generate transient load currents during the actual conversion process. A low source impedance at high frequencies minimizes the errors produced by these effects. Second, the drive amplifier provides the necessary gain and level shifting to match the signal to the ADC input voltage range
FUNCTIONS OF THE ADC DRIVE AMPLIFIER Buffer the analog signal from the ADC input ADC input may not be a constant high impedance ADC input may generate transient loads Provide other functions: Gain Level Shifting If the ADC input is constant high impedance with no transient loading, do not use a buffer amplifier unless required for gain or level shifting!! Fiqure 4.11 The S/(N+D) plot of the ADC should generally be used as the first selection criterion for the drive amplifier. If the Total Harmonic Distortion Plus Noise(THD+N)of the drive amplifier is always 6 to 10db better than the S/(N+D)of the adC over the frequency range of interest, then the overall degradation in S/(N+D)caused by the amplifier will be limited to between approximately 0.5dB and ldb, respectively. This will be illustrated using two state of the art components: the AD9022 12 bit, 20MSPS ADC and the AD9631 op amp a block diagram of the AD9022 is shown in Figure 4.12, and key specifications in Figure 4.13. AD9631/AD9632 key specifications are given in Figure 4.14 The AD9022 employs a three- pass subranging architecture and digital error correction. The analog input is applied to a 300Q2 attenuator and passed to the sampling bridge of the first internal track-and-hold amplifier (T/H). The held value of the first T/H is applied to a 5-bit flash converter and a second T/H. The 5-bit flash converter resolves the most significant bits(MSBs)of the held analog voltage. These 5 bits are reconstructed via a 5-bit dac and subtracted from the original T/h output signal to form a residue signal. a second T/H holds the amplified residue signal while it is encoded with a second 5-bit flash ADC. Again, the 5-bits are reconstructed and subtracted from the second T/H output to form a residue signal. This residue is amplified and encoded with a 4-bit flash adc to provide the 3 least significant bits (LSBs)of the digital output and one bit of error correction. The digital error correction logic combines the data from the three flash converters and presents the result as a 12-bit parallel digital word. The output stage is TTL(AD9022), or ECL D9023) Output data can be strobed on the rising edge of the ENcode command
1 2 FUNCTIONS OF THE ADC DRIVE AMPLIFIER Buffer the analog signal from the ADC input: ADC input may not be a constant high impedance ADC input may generate transient loads Provide other functions: Gain Level Shifting If the ADC input is constant high impedance with no transient loading, do not use a buffer amplifier unless required for gain or level shifting!! Figure 4.11 The S/(N+D) plot of the ADC should generally be used as the first selection criterion for the drive amplifier. If the Total Harmonic Distortion Plus Noise (THD+N) of the drive amplifier is always 6 to 10dB better than the S/(N+D) of the ADC over the frequency range of interest, then the overall degradation in S/(N+D) caused by the amplifier will be limited to between approximately 0.5dB and 1db, respectively. This will be illustrated using two state of the art components: the AD9022 12 bit, 20MSPS ADC and the AD9631 op amp. A block diagram of the AD9022 is shown in Figure 4.12, and key specifications in Figure 4.13. AD9631/AD9632 key specifications are given in Figure 4.14. The AD9022 employs a three-pass subranging architecture and digital error correction. The analog input is applied to a 300W attenuator and passed to the sampling bridge of the first internal track-and-hold amplifier (T/H). The held value of the first T/H is applied to a 5-bit flash converter and a second T/H. The 5-bit flash converter resolves the most significant bits (MSBs) of the held analog voltage. These 5 bits are reconstructed via a 5-bit DAC and subtracted from the original T/H output signal to form a residue signal. A second T/H holds the amplified residue signal while it is encoded with a second 5-bit flash ADC. Again, the 5-bits are reconstructed and subtracted from the second T/H output to form a residue signal. This residue is amplified and encoded with a 4-bit flash ADC to provide the 3 least significant bits (LSBs) of the digital output and one bit of error correction. The digital error correction logic combines the data from the three flash converters and presents the result as a 12-bit parallel digital word. The output stage is TTL (AD9022), or ECL (AD9023). Output data can be strobed on the rising edge of the ENCODE command
AD9022 12-BIT 20MSPS SAMPLING ADC NALOG ADC INPUT DIGITAL CORRECTION ENCODE DAC 052V Figure 4.12 AD9022 ADC KEY SPECIFICATIONS 12-bit, 20MSPS Sampling ADC TTL Outputs(AD9023 has ECL outputs) n-Chip reference and SHA High Spurious Free Dynamic Range(SFDR) 76dB 1MHz Input fs= 20MSPS 74dB 96MHz Input f. 20MSPS Analog Input Bandwidth: 110MHz Well-Behaved analog input with no transients Input Range: +1.024V, Input Impedance: 300Q2, 5pF Dual Supplies (+5,-5.2V), 1.4W Power Dissipation Figure 4.13
1 3 AD9022 12-BIT, 20MSPS SAMPLING ADC Figure 4.12 AD9022 ADC KEY SPECIFICATIONS 12-bit, 20MSPS Sampling ADC TTL Outputs (AD9023 has ECL outputs) On-Chip reference and SHA High Spurious Free Dynamic Range (SFDR): 76dB @ 1MHz Input fs = 20MSPS 74dB @ 9.6MHz Input fs = 20MSPS Analog Input Bandwidth: 110MHz Well-Behaved analog input with no transients Input Range: 1.024V, Input Impedance: 300 , 5pF Dual Supplies (+5, -5.2V), 1.4W Power Dissipation Figure 4.13
AD9632 OP AMP KEY SPECIFICATIONS Current-Feedback performance with voltage-feedback amps Small Signal Bandwidth 320MHz(AD9631,G= 250MHz(AD9632,G= Low Distortion -113dBc 1MHz 95dBc a 5Mhz 72dBc 20MHz Slew Rate: 1300v/gs Settling Time 16ns to 0.01%, 2V step Low Noise: Voltage: 7nV/Hz, Current: 2pA//Hz +3v to+5V Supply Operation, 17mA Supply Current Figure 4.14 Figure 4.15 shows the THD+N of the AD9631 drive amplifier superimposed on the S/(N+D) plot for the AD9022 ADC(12-bits, 20MSPS). Notice that the amplifier THD+ Nis at least 10dB better than the ADC S/(N+D) for input frequencies up to about 10MHz(the Nyquist frequency). In performing this comparison, it is important that the data for the op amp be obtained under the final operating conditions encountered in the actual circuit, i.e., gain, signal level, power supply voltage, etc. AD9022 ADC S/(N+D)AND AD9631 OP AMP THD+N PLOTTED AS A FUNCTION OF INPUT FREQUENCY 1. E 20MSPS AD9631 AD9022 AD9631 THD+N AD9022 SI(N+D) MAX INPUT FREQUENCY (MHz) Figure 4.15
1 4 AD9632 OP AMP KEY SPECIFICATIONS Current-Feedback performance with voltage-feedback amps Small Signal Bandwidth: 320MHz (AD9631, G = +1) 250MHz (AD9632, G = +2) Low Distortion: -113dBc @ 1MHz - 95dBc @ 5Mhz - 72dBc @ 20MHz Slew Rate: 1300V / s Settling Time: 16ns to 0.01%, 2V step Low Noise: Voltage: 7nV/ Hz, Current: 2pA/ Hz 3V to 5V Supply Operation, 17mA Supply Current Figure 4.14 Figure 4.15 shows the THD+N of the AD9631 drive amplifier superimposed on the S/(N+D) plot for the AD9022 ADC (12-bits, 20MSPS). Notice that the amplifier THD+ N is at least 10dB better than the ADC S/(N+D) for input frequencies up to about 10MHz (the Nyquist frequency). In performing this comparison, it is important that the data for the op amp be obtained under the final operating conditions encountered in the actual circuit, i.e., gain, signal level, power supply voltage, etc. AD9022 ADC S/(N+D) AND AD9631 OP AMP THD+N PLOTTED AS A FUNCTION OF INPUT FREQUENCY Figure 4.15
While s/(N+D)and THD+N are useful ac performance indicators, there are a number of applications where low distortion is more important than low noise. In spectral analysis using FFTs, or other applications where averaging techniques can be used to reduce the effects of noise, the amplifier Thd and the adc distortion (generally SFDR) should be used as the selection criteria. These characteristics should be plotted on the same scale, and the drive amplifier THd should be at least 6 to 10dB better than the ADC sFDR over the frequency range of interest. Such a plot for the AD9631 op amp and the ad9022 ADC is shown in Figure 4.16 AD9022 ADC SFDR AND AD9631 OP AMP THD PLOTTED AS A FUNCTION OF INPUT FREQUENCY H 20MSPS AD9631 THD AD2022 SFDR MAXIMUM FREQUENCY INPUT FREQUENCY(MHz) Figure 4.16 The above ac selection criterion works well if the adc input is relatively benign, but may give overly optimistic results if the input impedance is signal dependent, or the input produces transient currents. The existence of either of these two conditions requires further investigation. The implications of signal-dependent input impedance will be demonstrated using a flash converter. Dealing with ADC input transient currents will be illustrated by examining a fast single-supply sampling ADC with a CMOs switched capacitor input stage DRIVING FLASH CONVERTERS a typical flash converter(Figure 4.17) generally exhibits a signal-dependent input impedance(often referred to as non-linear input impedance), where the effective input capacitance is a function of signal level. The signal-dependent capacitance can be modeled as the junction capacitance of a diode, Ci. At the negative end of the all the parallel comparators in the flash converter are"off, and the capaci is low(modeled by a reverse-biased diode). At the positive end of the input all comparators are"on", thereby increasing the effective input capacitance(modeled by a zero-biased diode). For the example in the diagram, the Spice model(Figure 4. 18)for the flash converter input under consideration is a
1 5 While S/(N+D) and THD+N are useful ac performance indicators, there are a number of applications where low distortion is more important than low noise. In spectral analysis using FFTs, or other applications where averaging techniques can be used to reduce the effects of noise, the amplifier THD and the ADC distortion (generally SFDR) should be used as the selection criteria. These characteristics should be plotted on the same scale, and the drive amplifier THD should be at least 6 to 10dB better than the ADC SFDR over the frequency range of interest. Such a plot for the AD9631 op amp and the AD9022 ADC is shown in Figure 4.16. AD9022 ADC SFDR AND AD9631 OP AMP THD PLOTTED AS A FUNCTION OF INPUT FREQUENCY Figure 4.16 The above ac selection criterion works well if the ADC input is relatively benign, but may give overly optimistic results if the input impedance is signal dependent, or the input produces transient currents. The existence of either of these two conditions requires further investigation. The implications of signal-dependent input impedance will be demonstrated using a flash converter. Dealing with ADC input transient currents will be illustrated by examining a fast single-supply sampling ADC with a CMOS switched capacitor input stage. DRIVING FLASH CONVERTERS A typical flash converter (Figure 4.17) generally exhibits a signal-dependent input impedance (often referred to as non-linear input impedance), where the effective input capacitance is a function of signal level. The signal-dependent capacitance can be modeled as the junction capacitance of a diode, Cj . At the negative end of the input range, all the parallel comparators in the flash converter are "off", and the capacitance is low (modeled by a reverse-biased diode). At the positive end of the input range, all comparators are "on", thereby increasing the effective input capacitance (modeled by a zero-biased diode). For the example in the diagram, the Spice model (Figure 4.18) for the flash converter input under consideration is a