NTERMODULATION DISTORTION (MD) 2=SECOND ORDER IMD PRODUCTS 3=THIRD ORDER IMD PRODUCTS NOTE: f1=5MHz, f2=6MHz 31 FREQUENCY: MHz Figure 4.4 If we plot the gain of an amplifier with a small signal of a few millivolts or tens of millivolts, we find that as we increase the input frequency, there is a frequency at which the gain has dropped by 3 dB. This frequency is the upper limit of the small signal bandwidth of the amplifier and is set by the internal pole(s)in the amplifier response. If we drive the same amplifier with a large signal so that the output stage swings with its full rated peak-to-peak output voltage, we may find that the upper 3dB point is at a lower frequency, being limited by the slew rate of the amplifier output stage. This high-level 3dB point defines the large signal bandwidth of an amplifier. When defining the large signal bandwidth of an amplifier, a number of variables must be considered, including the power supply, the output amplitude(if slew rate is the only limiting factor, it is obvious that if the large signal amplitude is halved the large signal bandwidth is doubled), and the load. Thus large signal bandwidth is a rather uncertain parameter in an amplifier, since it depends on so the maximum output swing at any particular frequency. ut slew rate and calculate e many uncontrolled variables- in cases where the large signal bandwidth is less tha the small signal bandwidth, it is better to define the outp In an ADC, however, the maximum signal swing is always full scale, and the load seen by the signal is defined. It is therefore quite reasonable to define the large signal bandwidth(or full-power bandwidth)of an ADC and report it on the data sheet. In some cases, the small signal bandwidth may also be
6 INTERMODULATION DISTORTION (IMD) Figure 4.4 If we plot the gain of an amplifier with a small signal of a few millivolts or tens of millivolts, we find that as we increase the input frequency, there is a frequency at which the gain has dropped by 3 dB. This frequency is the upper limit of the small signal bandwidth of the amplifier and is set by the internal pole(s) in the amplifier response. If we drive the same amplifier with a large signal so that the output stage swings with its full rated peak-to-peak output voltage, we may find that the upper 3dB point is at a lower frequency, being limited by the slew rate of the amplifier output stage. This high-level 3dB point defines the large signal bandwidth of an amplifier. When defining the large signal bandwidth of an amplifier, a number of variables must be considered, including the power supply, the output amplitude (if slew rate is the only limiting factor, it is obvious that if the large signal amplitude is halved, the large signal bandwidth is doubled), and the load. Thus large signal bandwidth is a rather uncertain parameter in an amplifier, since it depends on so many uncontrolled variables - in cases where the large signal bandwidth is less than the small signal bandwidth, it is better to define the output slew rate and calculate the maximum output swing at any particular frequency. In an ADC, however, the maximum signal swing is always full scale, and the load seen by the signal is defined. It is therefore quite reasonable to define the large signal bandwidth (or full-power bandwidth) of an ADC and report it on the data sheet. In some cases, the small signal bandwidth may also be given
ADC LARGE SIGNAL (OR FULL POWER) BANDWIDTH With Small Signal, the Bandwidth of a Circuit is limited by its verall Frequency Response. At High Levels of Signal the Slew Rate of Some Stage May Control the Upper Frequency Limit. In Amplifiers There are so many Variables that Large Signal Bandwidth needs to be Redefined in every Individual Case, and Slew Rate is a more Useful parameter for a data sheet In ADCs the Maximum Signal Swing is the ADC's Full Scale Span, and is therefore Defined, so Full Power Bandwidth (FPBw) may Appear on the Data sheet. HoWEVER the FPBW Specification Says Nothing About Distortion Levels. Effective Number of Bits(ENoB )is Much More Useful in Practical Applications. Figure 4.5 However, the large signal bandwidth tells us the frequency at which the amplitude response of the AdC drops by 3dB- it tells us nothing at all about the relationship between distortion and frequency. If we study the behavior of an ADC as its input frequency is increased, we discover that, in general, noise and distortion increase with increasing frequency This reduces the resolution that we can obtain from the If we draw a graph of the ratio of signal-to-noise plus distortion(S/N+D)against its input frequency, we find a much more discouraging graph than that of its frequency response. The ratio of S/N+D can be expressed in dB or as effective number of bits (ENOB)as discussed above. As we have seen, the snr of a perfect N-bit ADC (with a full scale sinewave input) is(6.02N+ 1.76)dB. a graph of ENOB against the resolution of the ADC can actually be used, but can sometimes show interestina e dc variations of input amplitude can be depressing when we see just how little of th features: the ADC in Figure 4.6, for instance has a larger ENOB for signals at 10% of fs at 1MHz than for FS signals of the same frequency a simple frequency response curve cannot have plots crossing in this way
7 ADC LARGE SIGNAL (OR FULL POWER) BANDWIDTH With Small Signal, the Bandwidth of a Circuit is limited by its Overall Frequency Response. At High Levels of Signal the Slew Rate of Some Stage May Control the Upper Frequency Limit. In Amplifiers There are so many Variables that Large Signal Bandwidth needs to be Redefined in every Individual Case, and Slew Rate is a more Useful Parameter for a Data Sheet. In ADCs the Maximum Signal Swing is the ADC’s Full Scale Span, and is therefore Defined, so Full Power Bandwidth (FPBW) may Appear on the Data Sheet. HOWEVER the FPBW Specification Says Nothing About Distortion Levels. Effective Number of Bits (ENOB) is Much More Useful in Practical Applications. Figure 4.5 However, the large signal bandwidth tells us the frequency at which the amplitude response of the ADC drops by 3dB - it tells us nothing at all about the relationship between distortion and frequency. If we study the behavior of an ADC as its input frequency is increased, we discover that, in general, noise and distortion increase with increasing frequency. This reduces the resolution that we can obtain from the ADC. If we draw a graph of the ratio of signal-to-noise plus distortion (S/N+D) against its input frequency, we find a much more discouraging graph than that of its frequency response. The ratio of S/N+D can be expressed in dB or as effective number of bits (ENOB) as discussed above. As we have seen, the SNR of a perfect N-bit ADC (with a full scale sinewave input) is (6.02N + 1.76)dB. A graph of ENOB against the variations of input amplitude can be depressing when we see just how little of the dc resolution of the ADC can actually be used, but can sometimes show interesting features: the ADC in Figure 4.6, for instance, has a larger ENOB for signals at 10% of FS at 1MHz than for FS signals of the same frequency. A simple frequency response curve cannot have plots crossing in this way
ADC GAIN AND ENOB VERSUS FREQUENCY SHOWS INPORTANCE OF ENOB SPECIFICATION FPBW- 1MHz GAIN (FS INPUm 10M ADC INPUT FREQUENCY(Hz) Figure 4.6 The causes of the loss of ENOB at higher input frequencies are varied. The linearity of the adC transfer function degrades as the input frequency increases, thereby causing higher levels of distortion. Another reason that the snr of an adc decreases with input frequency may be deduced from Figure 4.7, which shows the effects of phase jitter on the sampling clock of an ADC. The phase jitter causes a voltage error which is a function of slew rate and results in an overall degradation in SNR as shown in Figure 4.8. This is quite serious, especially at higher input/output frequencies. Therefore, extreme care must be taken to minimize phase noise in the sampling/reconstruction clock of any sampled data system. This care must extend to ll aspects of the clock signal: the oscillator itself for example, a 555 timer is absolutely inadequate but even a quartz crystal oscillator can give problems if it uses an active device which shares a chip with noisy logic); the transmission path (these clocks are very vulnerable to interference of all sorts), and phase noise introduced in the ADC or DAC. A very common source of phase noise in converter circuitry is aperture jitter in the integral sample-and-hold(SHA)circuitry
8 ADC GAIN AND ENOB VERSUS FREQUENCY SHOWS INPORTANCE OF ENOB SPECIFICATION Figure 4.6 The causes of the loss of ENOB at higher input frequencies are varied. The linearity of the ADC transfer function degrades as the input frequency increases, thereby causing higher levels of distortion. Another reason that the SNR of an ADC decreases with input frequency may be deduced from Figure 4.7, which shows the effects of phase jitter on the sampling clock of an ADC. The phase jitter causes a voltage error which is a function of slew rate and results in an overall degradation in SNR as shown in Figure 4.8. This is quite serious, especially at higher input/output frequencies. Therefore, extreme care must be taken to minimize phase noise in the sampling/reconstruction clock of any sampled data system. This care must extend to all aspects of the clock signal: the oscillator itself ( for example, a 555 timer is absolutely inadequate, but even a quartz crystal oscillator can give problems if it uses an active device which shares a chip with noisy logic); the transmission path (these clocks are very vulnerable to interference of all sorts), and phase noise introduced in the ADC or DAC. A very common source of phase noise in converter circuitry is aperture jitter in the integral sample-and-hold (SHA) circuitry
EFFECTS OF APERATURE AND SAMPLING CLOCK JITTER ANALOG d A RMS APERTURE JITTER ERROR HELD OUTPUT RMS APERTURE JITTER HOLD TRACK igure 4.7 SNR DUE TO SAMPLING CLOCK JITTER (t) SNR= 20 log FULLSCALE SINEWAVE INPUT FREQUENCY (MHz) Figure 4.8 a decade or so ago, sampling ADCs were built up from a separate Sha and ADC Interface design was difficult, and a key parameter was aperture jitter in the Sha Today, most sampled data systems use sampling ADCs which contain an integral SHA. The aperture jitter of the Sha may not be specified as such, but this is not a cause of concern if the SNR or ENOB is clearly specified, since a guarantee of a specific SNR is an implicit guarantee of an adequate aperture jitter specification However, the use of an additional high-performance Sha will sometimes improve
9 EFFECTS OF APERATURE AND SAMPLING CLOCK JITTER Figure 4.7 SNR DUE TO SAMPLING CLOCK JITTER (tj ) Figure 4.8 A decade or so ago, sampling ADCs were built up from a separate SHA and ADC. Interface design was difficult, and a key parameter was aperture jitter in the SHA. Today, most sampled data systems use sampling ADCs which contain an integral SHA. The aperture jitter of the SHA may not be specified as such, but this is not a cause of concern if the SNR or ENOB is clearly specified, since a guarantee of a specific SNR is an implicit guarantee of an adequate aperture jitter specification. However, the use of an additional high-performance SHA will sometimes improve
the high-frequency enob of a sampling AdC, and may be more cost-effective than replacing the adC with a more expensive one It should be noted that there is also a fixed component which makes up the AdC aperture time. This component, usually called effective aperture delay time, does ne produce an error. It simply results in a time offset between the time the adc is asked to sample and when the actual sample takes place(see Figure 4.9).The variation or tolerance placed on this parameter from part to part is important in simultaneous sampling applications or other applications such as I and Q demodulation where several ADCs are required to track each other EFFECTIVE APERATURE DELAY TIME ANALOG INPUT ZERO CROSSING SINEWAVE SAMPLING CLOCK Figure 4.9 The distortion produced by an AdC or DAC cannot be analyzed in terms of second and third-order intercepts, as in the case of an amplifier. This is because there are two components of distortion in a high performance data converter. One component is due to the non-linearity associated with the analog circuits within the converter This non-linearity has the familiar"bow" or"s-shaped curve shown in Figure 4.10 (t may be polynomial or logarithmic in form). The distortion associated with this type of non-linearity is sometimes referred to as soft distortion and produces low order distortion products. This component of distortion behaves in the traditional manner, and is a function of signal level. In a practical data converter, however, the soft distortion is usually much less than the other component of distortion, which is function is more likely to have discrete points of discontinuity across the signar er due to the differential nonlinearity of the transfer function. The converter tran range as shown in Figure 4.10
1 0 the high-frequency ENOB of a sampling ADC, and may be more cost-effective than replacing the ADC with a more expensive one. It should be noted that there is also a fixed component which makes up the ADC aperture time. This component, usually called effective aperture delay time, does not produce an error. It simply results in a time offset between the time the ADC is asked to sample and when the actual sample takes place (see Figure 4.9). The variation or tolerance placed on this parameter from part to part is important in simultaneous sampling applications or other applications such as I and Q demodulation where several ADCs are required to track each other. EFFECTIVE APERATURE DELAY TIME Figure 4.9 The distortion produced by an ADC or DAC cannot be analyzed in terms of second and third-order intercepts, as in the case of an amplifier. This is because there are two components of distortion in a high performance data converter. One component is due to the non-linearity associated with the analog circuits within the converter. This non-linearity has the familiar "bow" or "s"-shaped curve shown in Figure 4.10. (It may be polynomial or logarithmic in form). The distortion associated with this type of non-linearity is sometimes referred to as soft distortion and produces loworder distortion products. This component of distortion behaves in the traditional manner, and is a function of signal level. In a practical data converter, however, the soft distortion is usually much less than the other component of distortion, which is due to the differential nonlinearity of the transfer function. The converter transfer function is more likely to have discrete points of discontinuity across the signal range as shown in Figure 4.10