SECTION 4 HIGH SPEED SAMPLING ADCS ADC Dynamic Considerations Selecting the Drive Amplifier Based on ADC Dynamic Performance Driving Flash Converters Driving the AD9050 Single-Supply ADC Driving ADCs with Switched Capacitor Inputs Gain Setting and Level Shifting External Reference Voltage generation ADC Input Protection and Clamping Applications for Clamping Amplifiers Noise Considerations in High Speed Sampling ADC Applications
1 SECTION 4 HIGH SPEED SAMPLING ADCs ADC Dynamic Considerations Selecting the Drive Amplifier Based on ADC Dynamic Performance Driving Flash Converters Driving the AD9050 Single-Supply ADC Driving ADCs with Switched Capacitor Inputs Gain Setting and Level Shifting External Reference Voltage Generation ADC Input Protection and Clamping Applications for Clamping Amplifiers Noise Considerations in High Speed Sampling ADC Applications
SECTION 4 HIGH SPEED SAMPLING ADCS Walt Kester Modern high speed sampling ADCs are designed to give low distortion and wide dynamic range in signal processing systems. Realization of specified performance levels depends upon a number of factors external to the ADC itself, including proper design of any necessary support circuitry. The analog input drive circuitry is especially critical, because it can degrade the inherent adc dynamic performance if not designed properly. Because of various process and design-related constraints, it is generally not possible to make the input of a high speed sampling adc totally well-behaved,i.e high impedance, low capacitance, ground-referenced, free from glitches, impervious to overdrive, etc. Therefore, the adc drive amplifier must provide excellent ac performance while driving what may be a somew hat hostile load (depending upon the particular ADC selected) The trend toward single-supply high speed designs adds additional constraints. The input voltage range of high speed single-supply ADCs may not be ground referenced (for valid design reasons), therefore level shifting with single-supply op amps(which may have limited common-mode input and output ranges) is usually required, unless the application allows the signal to be ac coupled. Although there is no standard high speed ADC input structure, this section addresses the most common ones and provides guidelines for properly designing the appropriate input drive circuitry. Some sampling ADCs also require external reference voltages. In other cases performance improvements can be realized by using an external reference in lieu of an internal one. It is equally important that these reference circuits be designed with utmost care, since they too affect the overall adC performance
2 SECTION 4 HIGH SPEED SAMPLING ADCS Walt Kester Modern high speed sampling ADCs are designed to give low distortion and wide dynamic range in signal processing systems. Realization of specified performance levels depends upon a number of factors external to the ADC itself, including proper design of any necessary support circuitry. The analog input drive circuitry is especially critical, because it can degrade the inherent ADC dynamic performance if not designed properly. Because of various process and design-related constraints, it is generally not possible to make the input of a high speed sampling ADC totally well-behaved, i.e., high impedance, low capacitance, ground-referenced, free from glitches, impervious to overdrive, etc. Therefore, the ADC drive amplifier must provide excellent ac performance while driving what may be a somewhat hostile load (depending upon the particular ADC selected). The trend toward single-supply high speed designs adds additional constraints. The input voltage range of high speed single-supply ADCs may not be ground referenced (for valid design reasons), therefore level shifting with single-supply op amps (which may have limited common-mode input and output ranges) is usually required, unless the application allows the signal to be ac coupled. Although there is no standard high speed ADC input structure, this section addresses the most common ones and provides guidelines for properly designing the appropriate input drive circuitry. Some sampling ADCs also require external reference voltages. In other cases, performance improvements can be realized by using an external reference in lieu of an internal one. It is equally important that these reference circuits be designed with utmost care, since they too affect the overall ADC performance
HIGH SPEED, LOW VOLTAGE SAMPLING ADCS Key Specifications for sampling ADCs ◆ Distortion Noise Distortion plus noise Effective Number of bits Bandwidth(Full Power and Small signal) Sampling Rate Modern Trends Low Power CMOS. BiMOS, or xFCB Processes Low Voltage 5V, +5V, +5V(Analog)/+3v(Digital) Input Voltage Ranges not always Ground-Referenced Analog Input Can Generate Transient Currents Figure 4.1 ADC DYNAMIC CONSIDERATIONS In order to make intelligent decisions regarding the input drive circuitry it is necessary to understand first exactly how the dynamic performance of the AdC is characterized Modern signal processing applications require ADCs with wide dynamic range, high bandwidth, low distortion, and low noise As well as having traditional de specifications(offset error, gain error, differential linearity error, and integral linearity error), sampling AD Cs(ADCs with an internal sample-and-hold function) are generally specified in terms of Signal-to-Noise Ratio(SNR, or S/N) Signal-to-Noise- Plus Distortion Ratio [S/(N+D), or SINADI, Effective Number of Bits (ENOB), Harmonic Distortion, Total Harmonic Distortion(tHD), Total Harmonic Distortion Plus Noise (THD+N), Intermodulation Distortion(IMD), and Spurious Free Dynamic Range(SFDR) Sampling adC data sheets may provide some, but not all of these ac specifications. The ac specifications are usually tested by applying spectrally pure sinewaves to the ADC and analyzing its output in the frequency domain with a Fast Fourier Transform(FFT). The process is similar to using an analog spectrum analyzer to measure the ac performance of an amplifier. Because of the quantization process, however, an adc produces some errors not found in amplifiers
3 HIGH SPEED, LOW VOLTAGE SAMPLING ADCs Key Specifications for sampling ADCs: Distortion Noise Distortion Plus Noise Effective Number of Bits Bandwidth (Full Power and Small Signal) Sampling Rate Modern Trends Low Power: CMOS, BiMOS, or XFCB Processes Low Voltage: 5V, +5V, +5V (Analog) / +3V (Digital) Input Voltage Ranges not always Ground-Referenced Analog Input Can Generate Transient Currents Figure 4.1 ADC DYNAMIC CONSIDERATIONS In order to make intelligent decisions regarding the input drive circuitry, it is necessary to understand first exactly how the dynamic performance of the ADC is characterized. Modern signal processing applications require ADCs with wide dynamic range, high bandwidth, low distortion, and low noise. As well as having traditional dc specifications (offset error, gain error, differential linearity error, and integral linearity error), sampling ADCs (ADCs with an internal sample-and-hold function) are generally specified in terms of Signal-to-Noise Ratio (SNR, or S/N), Signal-to-Noise-Plus Distortion Ratio [S/(N+D), or SINAD], Effective Number of Bits (ENOB), Harmonic Distortion, Total Harmonic Distortion (THD), Total Harmonic Distortion Plus Noise (THD+N), Intermodulation Distortion (IMD), and Spurious Free Dynamic Range (SFDR). Sampling ADC data sheets may provide some, but not all of these ac specifications. The ac specifications are usually tested by applying spectrally pure sinewaves to the ADC and analyzing its output in the frequency domain with a Fast Fourier Transform (FFT). The process is similar to using an analog spectrum analyzer to measure the ac performance of an amplifier. Because of the quantization process, however, an ADC produces some errors not found in amplifiers
ADC DYNAMIC PERFORMANCE SPECIFICATIONS Distortion Specifications:(Narrowband) Harmonic Distortion Total Harmonic Distortion(THD) Spurious Free Dynamic Range(SFDR) Intermodulation Distortion(IMD), Two-Tone Input Noise Specifications: dc to fs /2 Signal-to-Noise Ratio without Harmonics(often called SNR, or S/N) Noise Plus Distortion Specifications: dc to fs /2 Signal-to-Noise and Distortion(S/N+D, SINAD), but often referred to as snr (check definition carefully when evaluating ADCs), often converted to Effective Bits (ENOB) Total Harmonic Distortion Plus Noise(THD N) Broadband Noise can be reduced by filtering or averaging Figure 4.2 An ideal N-bit ADC, sampling at a rate fs, produces quantization noise having an rms value of q/(sqrt 12)measured in the Nyquist bandwidth dc to f/2, where q is the weight of the Least Significant Bit (LSB). The value of q is obtained by dividing the full scale input range of the adC by the number of quantization levels, 2 N. For example, an ideal 10-bit ADC with a 2.048V peak-to-peak input range has 2 10 1024 quantization levels, an LSB of 2mv, and an rms quantization noise of 2mV/(sqrt 12)=577uV rms The derivation of the theoretical value of quantization noise, q/(sqrt 12), makes the assumption that the quantization noise is not correlated in any fashion to the input signal, and may therefore be treated as Gaussian noise. This is normally true but in certain cases where the input sinewave frequency happens to be an exact submultiple of the sampling rate, the quantization noise may tend to be concentrated at the harmonics of the input signal, even though the rms value is still approximately q/(sqrt 12) Another way to express quantization noise is to convert it into a Signal-to-Noise ratio by dividing the rms value of the input sinewave by the rms value of the quantization noise. Normally, this is measured with a full scale input sinewave, and the expression relating the two is given by the well-known equation, SNR= 6.02N +176dB An actual adC will produce noise in excess of the theoretical quantization noise, as to calculate the rms value of all the distortion and noise products, and the actulay ed rell as distortion products caused by a non-linear transfer function. An FFT is us
4 ADC DYNAMIC PERFORMANCE SPECIFICATIONS Distortion Specifications: (Narrowband) Harmonic Distortion Total Harmonic Distortion (THD) Spurious Free Dynamic Range (SFDR) Intermodulation Distortion (IMD), Two-Tone Input Noise Specifications: dc to fs / 2 Signal-to-Noise Ratio without Harmonics (often called SNR, or S/N) Noise Plus Distortion Specifications: dc to fs / 2 Signal-to-Noise and Distortion (S/N+D, SINAD), but often referred to as SNR (check definition carefully when evaluating ADCs), often converted to Effective Bits (ENOB) Total Harmonic Distortion Plus Noise (THD + N) Broadband Noise can be reduced by filtering or averaging Figure 4.2 An ideal N-bit ADC, sampling at a rate fs , produces quantization noise having an rms value of q/(sqrt 12) measured in the Nyquist bandwidth dc to fs /2, where q is the weight of the Least Significant Bit (LSB). The value of q is obtained by dividing the full scale input range of the ADC by the number of quantization levels, 2^N. For example, an ideal 10-bit ADC with a 2.048V peak-to-peak input range has 2^10 = 1024 quantization levels, an LSB of 2mV, and an rms quantization noise of 2mV/(sqrt 12) = 577µV rms. The derivation of the theoretical value of quantization noise, q/(sqrt 12), makes the assumption that the quantization noise is not correlated in any fashion to the input signal, and may therefore be treated as Gaussian noise. This is normally true, but in certain cases where the input sinewave frequency happens to be an exact submultiple of the sampling rate, the quantization noise may tend to be concentrated at the harmonics of the input signal, even though the rms value is still approximately q/(sqrt 12). Another way to express quantization noise is to convert it into a Signal-to-Noise ratio by dividing the rms value of the input sinewave by the rms value of the quantization noise. Normally, this is measured with a full scale input sinewave, and the expression relating the two is given by the well-known equation, SNR = 602 . N + 176. dB. An actual ADC will produce noise in excess of the theoretical quantization noise, as well as distortion products caused by a non-linear transfer function. An FFT is used to calculate the rms value of all the distortion and noise products, and the actual
signal-to-noise- plus-distortion, S/(N+D), is computed. The above equation is solved for N, yielding the well-known expression for Effective Number of Bits, ENOB ENOB S/(N+ D)ACTUAL -176dB 602 For example, if a 10-bit ADC has an actual measured S/(N+D)of 56dB(theoretical would be 61.96dB), then it will have 9 effective bits, i.e., the non-ideal 10-bit ADO yields the same performance as an ideal 9-bit one EFFECTIVE NUMBER OF BITS(ENOB INDICATES OVERALL DYNAMIC PERFORMANCE OF ADCs S/(N+D)=6.02N+1.76dB(Theoretical) ADC ACHIEVES S/(N+D)=XdB(Actual) ENOB=(XdB-1.76dB)/(6.02dB) ENOB Includes Effects of all noise and distortion in the bandwidth dc to f/2 Figure 4.3 Even well-designed sampling ADCs have non-linearities which contribute to non ideal low frequency performance, and additionally, performance degrades as the input frequency is increased. A useful way to evaluate the ac performance of ADCs is to plot Signal-to-Noise Plus Distortion, S/(N+D), (or convert it to eNOB) as a function of input frequency. This measurement is somewhat all-inclusive and includes the effects of both noise and distortion products In some instances, sNR may be specified both with and without the distortion products, and in other cases, distortion may be specified separately, either as individual harmonic components, or as total harmonic distortion ( THD). Spurious and is the ratio of the signal level to the worst frequency spur under a given setor G Free Dynamic Range(SFDR) is simply another way of describing distortion product conditions. Intermodulation Distortion(IMD)is measured by applying two tones(F1 and F2)to the adc and determining the ratio of the power in one of the tones to the various IMD as shown in Figure 4.4. Unless otherwise specified, the third-order products which occur at the frequencies 2F1-F2 and 2F2-Fl are the ones used i the measurement because they lie close to the original tones and are difficult te filter
5 signal-to-noise-plus-distortion, S/(N+D), is computed. The above equation is solved for N, yielding the well-known expression for Effective Number of Bits, ENOB: ENOB S N D ACTUAL dB = / ( + ) - . . 176 602 . For example, if a 10-bit ADC has an actual measured S/(N+D) of 56dB (theoretical would be 61.96dB), then it will have 9 effective bits, i.e., the non-ideal 10-bit ADC yields the same performance as an ideal 9-bit one. EFFECTIVE NUMBER OF BITS (ENOB) INDICATES OVERALL DYNAMIC PERFORMANCE OF ADCs S/(N+D) = 6.02N + 1.76dB (Theoretical) ADC ACHIEVES S/(N+D) = XdB (Actual) ENOB = (XdB - 1.76dB) / (6.02dB) ENOB Includes Effects of All Noise and Distortion in the bandwidth DC to fs /2 Figure 4.3 Even well-designed sampling ADCs have non-linearities which contribute to nonideal low frequency performance, and additionally, performance degrades as the input frequency is increased. A useful way to evaluate the ac performance of ADCs is to plot Signal-to-Noise Plus Distortion, S/(N+D), (or convert it to ENOB) as a function of input frequency. This measurement is somewhat all-inclusive and includes the effects of both noise and distortion products. In some instances, SNR may be specified both with and without the distortion products, and in other cases, distortion may be specified separately, either as individual harmonic components, or as total harmonic distortion (THD). Spurious Free Dynamic Range (SFDR) is simply another way of describing distortion products and is the ratio of the signal level to the worst frequency spur, under a given set of conditions. Intermodulation Distortion (IMD) is measured by applying two tones (F1 and F2) to the ADC and determining the ratio of the power in one of the tones to the various IMD as shown in Figure 4.4. Unless otherwise specified, the third-order products which occur at the frequencies 2F1 – F2 and 2F2 – F1 are the ones used in the measurement because they lie close to the original tones and are difficult to filter