PACKAGE my gsim logic IS TYPE my_qsim_state Is(X,0,1,2), SUBTYPE my qsim value Is qsim state state RANGE'X TO 1 TYPE my_qsim_12state IS(SXR, SXZ, SXS SXI SOR SOZ. SOI, SIR SIZ, SIS, SID; FUNCtION my gsim state from(val: my qsim 12state) RETURN my qsim state END my gsim logic, USE my qsim logic. ALL, ENTITY and2 gate IS GENERIC(OutI rs, Outl fl: time: =0 ns) PORT (inO, inl: IN my qsim 12state outl: OUT my qsim 12state) END and2 gate
PACKAGE my_qsim_logic IS TYPE my_qsim_state IS (‘X’, ‘0’, ‘1’, ‘Z’); SUBTYPE my_qsim_value IS qsim_state_state RANGE ‘X’ TO ‘1’; TYPE my_qsim_12state IS (SXR, SXZ, SXS, SXI, S0R, S0Z, S0S, S0I, S1R, S1Z, S1S, S1I); FUNCTION my_qsim_state_from (val: my_qsim_12state) RETURN my_qsim_state; END my_qsim_logic; USE my_qsim_logic. ALL; ENTITY and2_gate IS GENERIC (Out1_rs, Out1_fl : time := 0 ns); PORT (in0, in1 : IN my_qsim_12state; out1 : OUT my_qsim_12state); END and2_gate;
arChiteCtuRE behave OF and2 gate IS BEGIN and inputs: PROCESS (inO, inl) BEGIN F((my qsim state from(inO)AND my qsim state from (inD))=1) then out1<=Sis aFter Outl rs ELSIF ((my gsim state from (inO) AND my gsim state from(inD)=0) then out1<= SOS AFTER Out1 f1 ELSIF (Outl rs >=Outl fI)THEN out1 < SXS AFtER Outl rs ELSE outl<=Sⅹ S AFTER Outl f END IF END PROCESS and inputs end beh
ARCHITECTURE behave OF and2_gate IS BEGIN and_inputs : PROCESS (in0, in1) BEGIN IF ((my_qsim_state_from (in0) AND my_qsim_state_from (in1)) = ‘1’) THEN out1 <= S1S AFTER Out1_rs; ELSIF ((my_qsim_state_from (in0) AND my_qsim_state_from(in1))=‘0’) THEN out1 <= S0S AFTER Out1_fl; ELSIF (Out1_rs >= Out1_fl) THEN out1 <= SXS AFTER Out1_rs; ELSE out1 <= SXS AFTER Out1_fl; END IF; END PROCESS and_inputs; END behave;
四、用 Generic参数化上升/降延时 对多值延时进行参数化 例:设在 package: my qsim extended中 有 function为 my qsim get time 可以将字符串根据定时模式转换为时间值
四、用Generic参数化上升/下降延时 对多值延时进行参数化 例：设在package : my_qsim_extended中 有function 为my_qsim_get_time， 可以将字符串根据定时模式转换为时间值
USE my lib. My qsim logic.AL;1b锁存器实体声明 USE my lib. My qsim extended. ALI ENTITY latch Is GENERIC O CONSTANT Data rise: string: =0, 0, 0 CONSTANT Data fall string: =0,0,0 CONSTANT Enable rise: string: 0,0,0 CONSTANT Enable fall string: =0, 0, 0 CONSTANT Timing mode: timing type: -typ)
USE my_lib. My_qsim_logic. ALL; 1bit锁存器实体声明 USE my_lib. My_qsim_extended. ALL; ENTITY latch IS GENERIC ( -- -- -- CONSTANT Data_rise : string := “0, 0, 0”; CONSTANT Data_fall : string := “0, 0, 0”; CONSTANT Enable_rise : string := “0, 0, 0”; CONSTANT Enable_fall : string := “0, 0, 0”; CONSTANT Timing_mode : timing_type := typ);
PORT(enable, data: IN my qsim state g out: OUT my qsim state) CONSTANT Data tplh: time: =my_qsim_ get_ time (Data rise, Timing_mode) CONSTANT Data tphl: time: -my qsim get time (Data fall, Timing mode) CONSTANT Enable tplh: time: -my qsim get time (Enable rise, Timing mode CONSTANT Enable tphl: time -my qsim get time (Enable fall, Timing mode) BEGIN END latch
PORT (enable, data : IN my_qsim_state; q_out : OUT my_qsim_state); CONSTANT Data_tplh : time := my_qsim_get_time (Data_rise, Timing_mode); CONSTANT Data_tphl : time := my_qsim_get_time (Data_fall, Timing_mode); CONSTANT Enable_tplh : time := my_qsim_get_time (Enable_rise, Timing_mode); CONSTANT Enable_tphl : time := my_qsim_get_time (Enable_fall, Timing_mode); BEGIN -- END latch;