Test Bench model latch Entity timing mode min, typ, max Test latch data 8.16.30 上升 data 下降 enabl 8,16,30 上升 enable 下降
Test Bench Model latch Entity timing_mode min, typ, max Test_latch data 8, 16, 30 上升 data 7, 14, 25 下降 enable 8, 16, 30 上升 enable 5, 7, 15 下降
LIBRARY my lib 测试台程序 USE my_lib. My_qsim _logic. ALL USE my lib. My qsim extended. ALL ENTITY test latch IS ENd test latch ARChiTECtUre test bed of test latch IS COMPONENT latchI GENERIC (En width, Da setup, Da hold: time Da rise, Da fall, En rise, En fall: string Timing mode: timing type PORT (Da, en: IN my qsim state q0: OUT my qsim state) END COMPONENT
LIBRARY my_lib; 测试台程序 USE my_lib. My_qsim_logic. ALL; USE my_lib. My_qsim_extended. ALL; ENTITY test_latch IS END test_latch ARCHITECTURE test_bed OF test_latch IS COMPONENT latch1 GENERIC (En_width, Da_setup, Da_hold : time; Da_rise, Da_fall, En_rise, En_fall : string; Timing_mode : timing_type); PORT (Da, en : IN my_qsim_state; q0 : OUT my_qsim_state); END COMPONENT;