嵌入固定延时参数 例 ENTITY and2 gate IS PORT (inO, inl: IN bit outl: oUt bit) END and2 gate ARCHITECTURE fixed delay Of and2 gate IS CONSTANT Typical delay: time: =8 ns: BEGIN outl < inO and inl aFTER Typical delay END fixed delay
一、嵌入固定延时参数 例： ENTITY and2_gate IS PORT (in0, in1 : IN bit; out1 : OUT bit); END and2_gate; ARCHITECTURE fixed_delay OF and2_gate IS CONSTANT Typical_delay : time := 8 ns; BEGIN out1 <= in0 AND in1 AFTER Typical_delay; END fixed_delay;
嵌入可变延时参数 例 LIBRARY my lib USE my lib. Logic example. ALL ENTITY and2 gate IS PORT (InO, inl IN my Isim LOGIC outI: OUT my Isim LOGIC) END and2 gate
二、嵌入可变延时参数 例： LIBRARY my_lib; USE my_lib. Logic_example. ALL; ENTITY and2_gate IS PORT (in0, in1 : IN my_lsim_LOGIC; out1 : OUT my_lsim_LOGIC); END and2_gate;
ARCHITECTURE variable delay Of and2 gate IS CONSTANT Tplh typ: time: =5 ns CONSTANT Tphl typ: time: =8ns BEGIN and inputs PROCESS (inO, in1) BEGIN IF (inO AND in1)=I' THEN outl<=1 AFTER Tplh typ ELSIF (inO AND in1)=0 THEN outl<=0 AFTER Tphl typ ELSIF ( Tph typ >=Tphl typ)THEN outl <=X AFTER TpIh typ ELSE outl<=X AFTER TphI typ END IF END PROCESS and inputs, END variable delay
ARCHITECTURE variable_delay OF and2_gate IS CONSTANT Tplh_typ : time := 5 ns; CONSTANT Tphl_typ : time := 8 ns; BEGIN and_inputs : PROCESS (in0, in1) BEGIN IF (in0 AND in1) = ‘1’ THEN out1 <= ‘1’ AFTER Tplh_typ; ELSIF (in0 AND in1) = ‘0’ THEN out1 <= ‘0’ AFTER Tphl_typ; ELSIF (Tplh_typ >= Tphl_typ) THEN out1 <= ‘X’ AFTER Tplh_typ; ELSE out1 <= ‘X’ AFTER Tphl_typ; END IF; END PROCESS and_inputs; END variable_delay;
用 generIc参数化模型 例 LIBRARY my lib USe my lib. my qsim logic. ALL ENTITY test and2 gate IS END test and2 gate
三、用generic参数化模型 例： LIBRARY my_lib; USE my_lib. my_qsim_logic. ALL; ENTITY test_and2_gate IS END test_and2_gate;
ARCHITECTURE test bench Of test and2 gate IS COMPONENT and2 GENERIC(RS, Fl: time) PORT (a, b: IN my qsim 12state OUT my gsim 12state) END COMPONENT FOR al: and2 USE ENTITY and2 gate( behav GENERIC MAP(RS, FD PORT MAP (a, b, c) SIGNAL X, y,z: my qsim 12state BEGIN al. and2 GENERIC MAP (7 ns, 10 ns) PORT MAP(X, y, Z); ENd test bench
ARCHITECTURE test_bench OF test_and2_gate IS COMPONENT and2 GENERIC (Rs, Fl : time); PORT (a, b : IN my_qsim_12state; c : OUT my_qsim_12state); END COMPONENT; FOR a1 : and2 USE ENTITY and2_gate(behav) GENERIC MAP (Rs, Fl) PORT MAP (a, b, c); SIGNAL x, y, z : my_qsim_12state; BEGIN a1 : and2 GENERIC MAP (7 ns, 10 ns); PORT MAP (x, y, z); END test_bench;