DescriptionSTM32F103xC,STM32F103xD,STM32F103xE2.3.6LCDparallelinterfaceTheFSMCcanbeconfiguredtointerface seamlesslywithmostgraphicLCDcontrollers.Itsupportsthe Intel 8080andMotorola6800modes,and isflexibleenoughtoadapttospecificLCD interfaces.ThisLCDparallelinterfacecapabilitymakes it easytobuildcost-effectivegraphicapplicationsusingLcDmodules with embeddedcontrollers orhigh-performancesolutionsusing externalcontrollers withdedicatedacceleration.2.3.7Nestedvectoredinterruptcontroller(NViC)TheSTM32F103xC,STM32F103xDandSTM32F103xEperformancelineembedsanestedvectoredinterruptcontrollerabletohandleupto6omaskableinterruptchannels(notincludingthe16 interrupt linesofCortexTM-M3)and16prioritylevels.CloselycoupledNViCgiveslowlatencyinterruptprocessingInterruptentryvectortableaddresspasseddirectlytothecore..CloselycoupledNViCcoreinterface.Allowsearlyprocessingof interrupts.Processingof latearrivinghigherpriorityinterruptsSupport for tail-chaining..Processor state automatically savedInterruptentryrestoredon interruptexit withno instructionoverhead.This hardware block provides flexible interrupt management features with minimal interruptlatency.2.3.8Externalinterrupt/eventcontroller(EXTI)Theexternal interrupt/eventcontrollerconsistsof19edgedetector linesusedtogenerateinterrupt/event requests.Each linecanbe independently configuredto selectthetriggerevent(risingedge,fallingedge,both)andcanbemaskedindependently.Apendingregistermaintains the status of the interrupt requests.The EXTI can detect an external line with apulsewidthshorterthantheInternalAPB2clockperiod.Upto112GPIOscanbeconnectedto the 16 external interrupt lines.2.3.9ClocksandstartupSystemclockselectionisperformedonstartup,howeverthe internalRC8MHzoscillatorisselectedasdefaultCPUclockonreset.Anexternal4-16MHzclockcanbeselected,irwhich case it ismonitoredforfailure.Iffailure isdetected,the system automatically switchesbacktotheinternalRCoscillator.Asoftwareinterruptisgeneratedifenabled.Similarly,fullinterruptmanagementofthePLLclockentryisavailablewhennecessary(forexamplewithfailureofan indirectlyusedexternal oscillator).Several prescalers allow the configuration of the AHB frequency,the high speed APB(APB2)andthelowspeedAPB(APB1)domains.ThemaximumfrequencyoftheAHBandthehighspeedAPBdomainsis72MHz.ThemaximumallowedfrequencyofthelowspeedAPBdomainis36MHz.SeeFigure2fordetailsontheclocktree.S16/123DocID14611Rev7
Description STM32F103xC, STM32F103xD, STM32F103xE 16/123 Doc ID 14611 Rev 7 2.3.6 LCD parallel interface The FSMC can be configured to interface seamlessly with most graphic LCD controllers. It supports the Intel 8080 and Motorola 6800 modes, and is flexible enough to adapt to specific LCD interfaces. This LCD parallel interface capability makes it easy to build costeffective graphic applications using LCD modules with embedded controllers or highperformance solutions using external controllers with dedicated acceleration. 2.3.7 Nested vectored interrupt controller (NVIC) The STM32F103xC, STM32F103xD and STM32F103xE performance line embeds a nested vectored interrupt controller able to handle up to 60 maskable interrupt channels (not including the 16 interrupt lines of Cortex™-M3) and 16 priority levels. ● Closely coupled NVIC gives low latency interrupt processing ● Interrupt entry vector table address passed directly to the core ● Closely coupled NVIC core interface ● Allows early processing of interrupts ● Processing of late arriving higher priority interrupts ● Support for tail-chaining ● Processor state automatically saved ● Interrupt entry restored on interrupt exit with no instruction overhead This hardware block provides flexible interrupt management features with minimal interrupt latency. 2.3.8 External interrupt/event controller (EXTI) The external interrupt/event controller consists of 19 edge detector lines used to generate interrupt/event requests. Each line can be independently configured to select the trigger event (rising edge, falling edge, both) and can be masked independently. A pending register maintains the status of the interrupt requests. The EXTI can detect an external line with a pulse width shorter than the Internal APB2 clock period. Up to 112 GPIOs can be connected to the 16 external interrupt lines. 2.3.9 Clocks and startup System clock selection is performed on startup, however the internal RC 8 MHz oscillator is selected as default CPU clock on reset. An external 4-16 MHz clock can be selected, in which case it is monitored for failure. If failure is detected, the system automatically switches back to the internal RC oscillator. A software interrupt is generated if enabled. Similarly, full interrupt management of the PLL clock entry is available when necessary (for example with failure of an indirectly used external oscillator). Several prescalers allow the configuration of the AHB frequency, the high speed APB (APB2) and the low speed APB (APB1) domains. The maximum frequency of the AHB and the high speed APB domains is 72 MHz. The maximum allowed frequency of the low speed APB domain is 36 MHz. See Figure 2 for details on the clock tree
STM32F103xC,STM32F103xD,STM32F103xEDescription2.3.10BootmodesAtstartup,bootpinsare usedto selectoneof threebootoptions:BootfromUserFlash?Boot fromSystem Memory1BootfromembeddedSRAMThebootloaderislocatedinSystemMemory.It isusedtoreprogramtheFlashmemorybyusing USART1.2.3.11PowersupplyschemesVpD = 2.0 to 3.6 V: external power supply for I/Os and the internal regulator..ProvidedexternallythroughVpppins.VssA,VpDA=2.0 to 3.6 V:external analog power supplies for ADC, Reset blocks,RCsand PLL (minimum voltage to be applied to VpDA is 2.4 V when the ADC is used). VpDAand VssAmust beconnectedtoVp andVss,respectively.VBAT = 1.8 to 3.6 V: power supply for RTC, external clock 32 kHz oscillator and backupregisters (through power switch)when Vp is notpresent.Formoredetailsonhowtoconnectpowerpins,refertoFigure12:Powersupplyscheme.2.3.12PowersupplysupervisorThedevicehasan integrated power-onreset(POR)/power-downreset(PDR)circuitry.It isalwaysactive,andensuresproperoperationstartingfrom/downto2V.Thedeviceremainsin reset mode when VpD is below a specified threshold, VpoR/PDR, without the need for anexternal reset circuit.Thedevicefeatures an embeddedprogrammable voltagedetector(PVD)thatmonitors theVpp/VpDA power supply and compares it to the VpvD threshold. An interrupt can begeneratedwhenVpppDAdropsbelowtheVpyDthresholdand/orwhenVpp/NpAishigherthan the Vpvp threshold. The interrupt service routine can then generate a warningmessageand/orputtheMCUintoasafestate.ThePVDisenabledbysoftware.RefertoTable12:EmbeddedresetandpowercontrolblockcharacteristicsforthevaluesofVPOR/PDR and VpVD-2.3.13Voltage regulatorTheregulatorhasthreeoperationmodes:main (MR),lowpower(LPR)andpowerdown.?MRis used inthenominal regulationmode (Run)LPRisusedintheStopmodesPowerdown is used in Standby mode:the regulator output is in high impedance:thekernel circuitry is powereddown, inducingzero consumption (butthe contents of theregistersandSRAMarelost)Thisregulatorisalwaysenabledafterreset.ItisdisabledinStandbymode.STDocID14611Rev717/123
STM32F103xC, STM32F103xD, STM32F103xE Description Doc ID 14611 Rev 7 17/123 2.3.10 Boot modes At startup, boot pins are used to select one of three boot options: ● Boot from User Flash ● Boot from System Memory ● Boot from embedded SRAM The boot loader is located in System Memory. It is used to reprogram the Flash memory by using USART1. 2.3.11 Power supply schemes ● VDD = 2.0 to 3.6 V: external power supply for I/Os and the internal regulator. Provided externally through VDD pins. ● VSSA, VDDA = 2.0 to 3.6 V: external analog power supplies for ADC, Reset blocks, RCs and PLL (minimum voltage to be applied to VDDA is 2.4 V when the ADC is used). VDDA and VSSA must be connected to VDD and VSS, respectively. ● VBAT = 1.8 to 3.6 V: power supply for RTC, external clock 32 kHz oscillator and backup registers (through power switch) when VDD is not present. For more details on how to connect power pins, refer to Figure 12: Power supply scheme. 2.3.12 Power supply supervisor The device has an integrated power-on reset (POR)/power-down reset (PDR) circuitry. It is always active, and ensures proper operation starting from/down to 2 V. The device remains in reset mode when VDD is below a specified threshold, VPOR/PDR, without the need for an external reset circuit. The device features an embedded programmable voltage detector (PVD) that monitors the VDD/VDDA power supply and compares it to the VPVD threshold. An interrupt can be generated when VDD/VDDA drops below the VPVD threshold and/or when VDD/VDDA is higher than the VPVD threshold. The interrupt service routine can then generate a warning message and/or put the MCU into a safe state. The PVD is enabled by software. Refer to Table 12: Embedded reset and power control block characteristics for the values of VPOR/PDR and VPVD. 2.3.13 Voltage regulator The regulator has three operation modes: main (MR), low power (LPR) and power down. ● MR is used in the nominal regulation mode (Run) ● LPR is used in the Stop modes. ● Power down is used in Standby mode: the regulator output is in high impedance: the kernel circuitry is powered down, inducing zero consumption (but the contents of the registers and SRAM are lost) This regulator is always enabled after reset. It is disabled in Standby mode
DescriptionSTM32F103xC,STM32F103xD,STM32F103xE2.3.14Low-powermodesTheSTM32F103xC,STM32F103xDandSTM32F103xEperformancelinesupports threelow-powermodestoachievethebestcompromisebetweenlowpowerconsumption,shortstartuptimeandavailablewakeupsources?SleepmodeIn Sleep mode, only the CPU is stopped. All peripherals continue to operate and canwakeuptheCPUwhenan interrupt/eventoccurs.Stop modeStopmodeachievesthe lowestpowerconsumptionwhileretainingthecontentofSRAMandregisters.Allclocksinthe1.8Vdomainarestopped,thePLL,theHSlRCand the HSEcrystal oscillators are disabled.The voltageregulator can also be puteitherinnormalorinlow-powermodeThedevicecanbewokenupfromStopmodebyanyoftheEXTI line.TheEXTI linesourcecan be oneofthe16external lines,thePVDoutput, theRTC alarmor theUSBwakeup.Standby modeTheStandbymodeisusedtoachievethelowestpowerconsumption.Theinternalvoltageregulator is switched off sothatthe entire1.8Vdomain is powered off.ThePLL,the HSI RC and theHSEcrystal oscillatorsare also switched off.After enteringStandbymode,SRAMandregister contents arelostexceptforregisters in theBackupdomain and Standby circuitry.ThedeviceexitsStandbymodewhenanexternalreset (NRSTpin),anIWDGreset,arisingedgeontheWKUPpin,oranRTCalarmoccurs.Note:TheRTC,theIWDG,andthecorrespondingclocksourcesarenotstoppedbyenteringStoporStandbymode.2.3.15DMATheflexible12-channelgeneral-purposeDMAs(7channelsforDMA1and5channelsforDMA2)areable tomanage memory-to-memory,peripheral-to-memoryand memory-toperipheral transfers.ThetwoDMAcontrollerssupportcircularbuffermanagement,removingtheneedforusercodeinterventionwhenthecontrollerreachestheendof thebuffer.EachchannelisconnectedtodedicatedhardwareDMArequests,withsupportforsoftwaretriggeroneachchannel.Configurationismadebysoftwareandtransfer sizesbetweensource anddestination are independent.TheDMAcan be usedwiththemain peripherals:SPI,I2c,USART,general-purpose,basicandadvanced-controltimersTIMx,DAC,i2s,SDIOandADC2.3.16RTC (real-time clock)and backup registersThe RTC and thebackup registers are supplied through a switch thattakes power either onVppsupplywhenpresentorthroughtheVBATpin.Thebackupregistersareforty-two16-bitregisters used to store 84 bytes of user application data when Vpp power is not present.Theyare not resetby a system or power reset,and they are notreset when the devicewakesupfromtheStandbymode.Thereal-timeclockprovidesa setof continuously running counterswhich canbeusedwithsuitablesoftwaretoprovideaclockcalendarfunction,andprovidesan alarm interruptandaS18/123Doc ID14611Rev7
Description STM32F103xC, STM32F103xD, STM32F103xE 18/123 Doc ID 14611 Rev 7 2.3.14 Low-power modes The STM32F103xC, STM32F103xD and STM32F103xE performance line supports three low-power modes to achieve the best compromise between low power consumption, short startup time and available wakeup sources: ● Sleep mode In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can wake up the CPU when an interrupt/event occurs. ● Stop mode Stop mode achieves the lowest power consumption while retaining the content of SRAM and registers. All clocks in the 1.8 V domain are stopped, the PLL, the HSI RC and the HSE crystal oscillators are disabled. The voltage regulator can also be put either in normal or in low-power mode. The device can be woken up from Stop mode by any of the EXTI line. The EXTI line source can be one of the 16 external lines, the PVD output, the RTC alarm or the USB wakeup. ● Standby mode The Standby mode is used to achieve the lowest power consumption. The internal voltage regulator is switched off so that the entire 1.8 V domain is powered off. The PLL, the HSI RC and the HSE crystal oscillators are also switched off. After entering Standby mode, SRAM and register contents are lost except for registers in the Backup domain and Standby circuitry. The device exits Standby mode when an external reset (NRST pin), an IWDG reset, a rising edge on the WKUP pin, or an RTC alarm occurs. Note: The RTC, the IWDG, and the corresponding clock sources are not stopped by entering Stop or Standby mode. 2.3.15 DMA The flexible 12-channel general-purpose DMAs (7 channels for DMA1 and 5 channels for DMA2) are able to manage memory-to-memory, peripheral-to-memory and memory-toperipheral transfers. The two DMA controllers support circular buffer management, removing the need for user code intervention when the controller reaches the end of the buffer. Each channel is connected to dedicated hardware DMA requests, with support for software trigger on each channel. Configuration is made by software and transfer sizes between source and destination are independent. The DMA can be used with the main peripherals: SPI, I2C, USART, general-purpose, basic and advanced-control timers TIMx, DAC, I2S, SDIO and ADC. 2.3.16 RTC (real-time clock) and backup registers The RTC and the backup registers are supplied through a switch that takes power either on VDD supply when present or through the VBAT pin. The backup registers are forty-two 16-bit registers used to store 84 bytes of user application data when VDD power is not present. They are not reset by a system or power reset, and they are not reset when the device wakes up from the Standby mode. The real-time clock provides a set of continuously running counters which can be used with suitable software to provide a clock calendar function, and provides an alarm interrupt and a
STM32F103xC,STM32F103xD,STM32F103xEDescriptionperiodic interrupt.Itisclockedbya32.768kHzexternal crystal,resonatororoscillator,theinternal lowpowerRCoscillatororthehigh-speedexternalclockdividedby128.Theinternal low-speedRChasatypical frequencyof 40kHz.TheRTCcanbecalibratedusinganexternal512Hzoutputtocompensateforanynaturalquartzdeviation.TheRTCfeaturesa32-bitprogrammablecounterforlongtermmeasurementusingtheCompareregistertogenerateanalarm.A20-bitprescaler is usedforthetimebase clockand isbydefaultconfiguredtogeneratea timebaseof1secondfromaclock at32.768kHz.2.3.17TimersandwatchdogsThehigh-densitySTM32F103xxperformance linedevices includeuptotwoadvanced-controltimers,uptofourgeneral-purposetimers,twobasictimers,twowatchdogtimers anda SysTick timer.Table 4 compares the features of the advanced-control, general-purpose and basic timers.Table 4.High-density timer feature comparisonCounterPrescalerDMArequestCounterCapture/compareComplementaryTimerresolutiontypefactorgenerationchannelsoutputsUp,Any integerTIM1,416-bitYesYesdown,between1TIM8up/downand65536TIM2,Up,Any integerTIM3,4No16-bitdown,Yesbetween1TIM4.up/downand65536TIM5Any integerTIM6,0UpYesNo16-bitbetween1TIM7and65536Advanced-controltimers(TIM1andTIM8)The two advanced-control timers (TIM1 and TIM8) can each be seen as a three-phasePWMmultiplexedon6channels.TheyhavecomplementaryPWMoutputswithprogrammableinserteddead-times.Theycanalsobeseenasa completegeneral-purposetimer.The4independentchannelscanbeusedfor:.Input captureOutput compare.PWM generation (edge or center-aligned modes)..One-pulsemodeoutputIf configured as a standard 16-bit timer, it has the samefeatures as theTiMx timer.Ifconfiguredas the16-bit PWMgenerator,it hasfullmodulationcapability (0-100%).Indebugmode,theadvanced-controltimercountercanbefrozenandthePwMoutputsdisabledtoturnoffanypowerswitchdrivenbytheseoutputs.Manyfeaturesaresharedwiththoseofthegeneral-purposeTiMtimerswhichhavethesame architecture.The advanced-control timer can therefore work together with the TIMtimers via the Timer Link featureforsynchronization or eventchainingA19/123DocID14611Rev7
STM32F103xC, STM32F103xD, STM32F103xE Description Doc ID 14611 Rev 7 19/123 periodic interrupt. It is clocked by a 32.768 kHz external crystal, resonator or oscillator, the internal low power RC oscillator or the high-speed external clock divided by 128. The internal low-speed RC has a typical frequency of 40 kHz. The RTC can be calibrated using an external 512 Hz output to compensate for any natural quartz deviation. The RTC features a 32-bit programmable counter for long term measurement using the Compare register to generate an alarm. A 20-bit prescaler is used for the time base clock and is by default configured to generate a time base of 1 second from a clock at 32.768 kHz. 2.3.17 Timers and watchdogs The high-density STM32F103xx performance line devices include up to two advancedcontrol timers, up to four general-purpose timers, two basic timers, two watchdog timers and a SysTick timer. Table 4 compares the features of the advanced-control, general-purpose and basic timers. Advanced-control timers (TIM1 and TIM8) The two advanced-control timers (TIM1 and TIM8) can each be seen as a three-phase PWM multiplexed on 6 channels. They have complementary PWM outputs with programmable inserted dead-times. They can also be seen as a complete general-purpose timer. The 4 independent channels can be used for: ● Input capture ● Output compare ● PWM generation (edge or center-aligned modes) ● One-pulse mode output If configured as a standard 16-bit timer, it has the same features as the TIMx timer. If configured as the 16-bit PWM generator, it has full modulation capability (0-100%). In debug mode, the advanced-control timer counter can be frozen and the PWM outputs disabled to turn off any power switch driven by these outputs. Many features are shared with those of the general-purpose TIM timers which have the same architecture. The advanced-control timer can therefore work together with the TIM timers via the Timer Link feature for synchronization or event chaining. Table 4. High-density timer feature comparison Timer Counter resolution Counter type Prescaler factor DMA request generation Capture/compare channels Complementary outputs TIM1, TIM8 16-bit Up, down, up/down Any integer between 1 and 65536 Yes 4 Yes TIM2, TIM3, TIM4, TIM5 16-bit Up, down, up/down Any integer between 1 and 65536 Yes 4 No TIM6, TIM7 16-bit Up Any integer between 1 and 65536 Yes 0 No
DescriptionSTM32F103xC,STM32F103xD,STM32F103xEGeneral-purposetimers(TIMx)There are up to 4 synchronizable general-purpose timers (TIM2, TIM3, TIM4 and TIM5)embeddedintheSTM32F103xC,STM32F103xDandSTM32F103xEperformancelinedevices.These timersarebasedona 16-bitauto-reload up/down counter,a16-bitprescalerandfeature4 independentchannels eachforinput capture/output compare,PWMorone-pulsemodeoutput.Thisgivesupto16input captures/output compares/PwMsonthelargestpackages.The general-purpose timers can work together with the advanced-control timer via the TimerLink featureforsynchronizationoreventchaining.Theircountercanbefrozen indebugmode.Anyofthegeneral-purposetimers canbe usedto generatePWM outputs.TheyallhaveindependentDMArequestgeneration.These timers are capable of handling quadrature (incremental) encoder signals and thedigital outputsfrom1to3hall-effectsensors.BasictimersTIM6andTIM7These timers are mainly used for DAC trigger generation. They can also be used as ageneric 16-bit time base.IndependentwatchdogTheindependentwatchdogis based ona 12-bitdowncounterand 8-bit prescaler.It isclocked from an independent40kHz internal RCand as it operates independently fromthemain clock, it canoperate inStopandStandbymodes.Itcanbeused eitherasa watchdogtoresetthedevicewhenaproblemoccurs,oras a free runningtimerforapplicationtimeoutmanagement. It is hardware or software configurable through the option bytes.The countercanbe frozen in debug mode.Window watchdogThewindowwatchdog is based ona7-bit downcounterthat can beset as free running.Itcanbe used asawatchdogtoresetthedevice whenaproblemoccurs.It is clockedfromthemainclock.Ithasanearlywarning interruptcapabilityandthecountercanbefrozen indebug mode.SysTicktimerThistimerisdedicatedtoreal-time operatingsystems,butcouldalsobeusedasa standarddowncounter.Itfeatures:A24-bitdown counter..Autoreload capability.Maskable system interrupt generation when the counter reaches 0..Programmableclocksource2cbus2.3.18Up to two 2C bus interfaces can operate in multimaster and slave modes. They can supportstandard andfastmodesThey support 7/10-bit addressing mode and 7-bit dual addressing mode (as slave). AhardwareCRCgeneration/verificationisembedded.TheycanbeservedbyDMAandtheysupportSMBus2.o/PMBus.S20/123Doc ID14611Rev7
Description STM32F103xC, STM32F103xD, STM32F103xE 20/123 Doc ID 14611 Rev 7 General-purpose timers (TIMx) There are up to 4 synchronizable general-purpose timers (TIM2, TIM3, TIM4 and TIM5) embedded in the STM32F103xC, STM32F103xD and STM32F103xE performance line devices. These timers are based on a 16-bit auto-reload up/down counter, a 16-bit prescaler and feature 4 independent channels each for input capture/output compare, PWM or onepulse mode output. This gives up to 16 input captures / output compares / PWMs on the largest packages. The general-purpose timers can work together with the advanced-control timer via the Timer Link feature for synchronization or event chaining. Their counter can be frozen in debug mode. Any of the general-purpose timers can be used to generate PWM outputs. They all have independent DMA request generation. These timers are capable of handling quadrature (incremental) encoder signals and the digital outputs from 1 to 3 hall-effect sensors. Basic timers TIM6 and TIM7 These timers are mainly used for DAC trigger generation. They can also be used as a generic 16-bit time base. Independent watchdog The independent watchdog is based on a 12-bit downcounter and 8-bit prescaler. It is clocked from an independent 40 kHz internal RC and as it operates independently from the main clock, it can operate in Stop and Standby modes. It can be used either as a watchdog to reset the device when a problem occurs, or as a free running timer for application timeout management. It is hardware or software configurable through the option bytes. The counter can be frozen in debug mode. Window watchdog The window watchdog is based on a 7-bit downcounter that can be set as free running. It can be used as a watchdog to reset the device when a problem occurs. It is clocked from the main clock. It has an early warning interrupt capability and the counter can be frozen in debug mode. SysTick timer This timer is dedicated to real-time operating systems, but could also be used as a standard down counter. It features: ● A 24-bit down counter ● Autoreload capability ● Maskable system interrupt generation when the counter reaches 0. ● Programmable clock source 2.3.18 I²C bus Up to two I²C bus interfaces can operate in multimaster and slave modes. They can support standard and fast modes. They support 7/10-bit addressing mode and 7-bit dual addressing mode (as slave). A hardware CRC generation/verification is embedded. They can be served by DMA and they support SMBus 2.0/PMBus