STM32F103xC,STM32F103xD,STM32F103xEDescription2.3.19Universalsynchronous/asynchronousreceivertransmitters(USARTs)TheSTM32F103xC,STM32F103xDandSTM32F103xEperformancelineembedsthreeuniversalsynchronous/asynchronousreceivertransmitters(USART1,USART2andUSART3)andtwouniversalasynchronousreceivertransmitters(UART4andUART5)Thesefiveinterfacesprovideasynchronouscommunication,IrDASIRENDECsupport,multiprocessorcommunicationmode,single-wirehalf-duplexcommunicationmodeandhaveLINMaster/Slave capability.TheUSART1 interfaceisabletocommunicateat speedsofupto4.5Mbit/s.Theotheravailable interfaces communicate at up to 2.25 Mbit/s.USART1,USART2 and USART3 also provide hardware management of the CTS and RTSsignals,SmartCardmode(ISO7816compliant)andSPl-likecommunicationcapability.AllinterfacescanbeservedbytheDMAcontrollerexceptforUART52.3.20Serial peripheral interface (SPI)UptothreeSPlsareabletocommunicateupto18Mbits/sinslaveandmastermodesinfull-duplexandsimplexcommunicationmodes.The3-bitprescalergives8mastermodefrequenciesandtheframeisconfigurableto8bitsor16bits.ThehardwareCRCgeneration/verification supports basic SD Card/MMC modes.All SPls can be served by the DMA controller.Inter-integratedsound (I?s)2.3.21Two standard IPs interfaces (multiplexed with SPI2 and SPI3) are available, that can beoperated inmasterorslavemode.These interfacescanbeconfiguredtooperatewith16/32bit resolution,as inputoroutputchannels.Audiosamplingfrequenciesfrom8kHzupto48kHzaresupported.Wheneitherorbothofthe12sinterfacesis/areconfiguredinmastermode,themasterclockcanbeoutputtotheexternalDAC/CODECat256timesthesamplingfrequency2.3.22SDIOAnSD/SDIO/MMChostinterfaceisavailable,thatsupportsMultiMediaCardSystemSpecification Version 4.2 in three different databus modes: 1-bit (default), 4-bit and 8-bit.Theinterfaceallowsdatatransferatupto48MHz in8-bitmode,and iscompliantwithSDMemoryCardSpecificationsVersion2.0TheSDIOCardSpecificationVersion2.oisalsosupportedwithtwodifferentdatabusmodes: 1-bit (default)and4-bit.The current version supports only one SD/SDIO/MMC4.2 card at any one time and a stackofMMC4.1orprevious.Inadditionto SD/SDIO/MMC,this interfaceisalsofullycompliant with theCE-ATAdigitalprotocol Rev1.1.2.3.23Controllerareanetwork(CAN)TheCANiscompliantwithspecifications2.0AandB(active)withabitrateupto1Mbit/s.Itcanreceiveandtransmitstandardframeswith11-bitidentifiersaswellasextendedframeswith29-bit identifiers.Ithasthreetransmitmailboxes,tworeceiveFiFOswith3stagesand14scalablefilterbanks.ST21/123DocID14611Rev7
STM32F103xC, STM32F103xD, STM32F103xE Description Doc ID 14611 Rev 7 21/123 2.3.19 Universal synchronous/asynchronous receiver transmitters (USARTs) The STM32F103xC, STM32F103xD and STM32F103xE performance line embeds three universal synchronous/asynchronous receiver transmitters (USART1, USART2 and USART3) and two universal asynchronous receiver transmitters (UART4 and UART5). These five interfaces provide asynchronous communication, IrDA SIR ENDEC support, multiprocessor communication mode, single-wire half-duplex communication mode and have LIN Master/Slave capability. The USART1 interface is able to communicate at speeds of up to 4.5 Mbit/s. The other available interfaces communicate at up to 2.25 Mbit/s. USART1, USART2 and USART3 also provide hardware management of the CTS and RTS signals, Smart Card mode (ISO 7816 compliant) and SPI-like communication capability. All interfaces can be served by the DMA controller except for UART5. 2.3.20 Serial peripheral interface (SPI) Up to three SPIs are able to communicate up to 18 Mbits/s in slave and master modes in full-duplex and simplex communication modes. The 3-bit prescaler gives 8 master mode frequencies and the frame is configurable to 8 bits or 16 bits. The hardware CRC generation/verification supports basic SD Card/MMC modes. All SPIs can be served by the DMA controller. 2.3.21 Inter-integrated sound (I2S) Two standard I2S interfaces (multiplexed with SPI2 and SPI3) are available, that can be operated in master or slave mode. These interfaces can be configured to operate with 16/32 bit resolution, as input or output channels. Audio sampling frequencies from 8 kHz up to 48 kHz are supported. When either or both of the I2S interfaces is/are configured in master mode, the master clock can be output to the external DAC/CODEC at 256 times the sampling frequency. 2.3.22 SDIO An SD/SDIO/MMC host interface is available, that supports MultiMediaCard System Specification Version 4.2 in three different databus modes: 1-bit (default), 4-bit and 8-bit. The interface allows data transfer at up to 48 MHz in 8-bit mode, and is compliant with SD Memory Card Specifications Version 2.0. The SDIO Card Specification Version 2.0 is also supported with two different databus modes: 1-bit (default) and 4-bit. The current version supports only one SD/SDIO/MMC4.2 card at any one time and a stack of MMC4.1 or previous. In addition to SD/SDIO/MMC, this interface is also fully compliant with the CE-ATA digital protocol Rev1.1. 2.3.23 Controller area network (CAN) The CAN is compliant with specifications 2.0A and B (active) with a bit rate up to 1 Mbit/s. It can receive and transmit standard frames with 11-bit identifiers as well as extended frames with 29-bit identifiers. It has three transmit mailboxes, two receive FIFOs with 3 stages and 14 scalable filter banks
DescriptionSTM32F103xC,STM32F103xD,STM32F103xE2.3.24Universal serial bus (USB)TheSTM32F103xC,STM32F103xDandSTM32F103xEperformancelineembedaUSBdeviceperipheral compatible withthe USB full-speed12Mbs.The USB interfaceimplementsafull-speed(12Mbit/s)functioninterface.Ithassoftware-configurableendpointsettingandsuspend/resumesupport.Thededicated48MHzclockisgeneratedfromtheinternal mainPLL (theclocksourcemustusea HSEcrystal oscillator).2.3.25GPiOs(general-purposeinputs/outputs)Each of the GPlO pins can beconfigured bysoftware as output (push-pullor open-drain),asinput (with or without pull-up or pull-down) or as peripheral alternate function. Most of theGPIOpinsaresharedwithdigitaloranalogalternatefunctions.AllGPIOsarehighcurrent-capable exceptforanalog inputs.TheI/Osalternatefunctionconfigurationcanbelockedifneededfollowingaspecificsequence in orderto avoid spurious writing to the I/Os registers.VOs on APB2with up to18MHz toggling speed2.3.26ADC (analog to digital converter)Three12-bitanalog-to-digitalconvertersareembeddedintoSTM32F103xC,STM32F103xDandSTM32F103xEperformancelinedevicesandeachADCsharesupto21externalchannels,performing conversionsinsingle-shotor scanmodes.Inscanmode,automaticconversionisperformedonaselectedgroupofanaloginputs.Additional logicfunctionsembedded intheADCinterfaceallow:Simultaneous sample and hold?Interleavedsampleandhold?.SingleshuntTheADCcanbeservedbytheDMAcontroller.Ananalogwatchdogfeatureallowsveryprecisemonitoringoftheconvertedvoltageofonesome orall selected channels.An interrupt is generated when the converted voltage isoutsidetheprogrammed thresholds.Theeventsgeneratedbythegeneral-purposetimers(TiMx)andtheadvanced-controltimers(TIM1andTIM8)canbeinternallyconnectedtotheADCstarttriggerand injectiortrigger,respectively,toallowtheapplicationto synchronizeA/D conversionandtimers.2.3.27DAC(digital-to-analogconverter)The two 12-bit bufferedDAC channels can be usedto converttwo digital signals intotwaanalog voltage signaloutputs.The chosendesign structure is composedof integratedresistorstrings andanamplifierin inverting configuration.S22/123Doc ID14611Rev7
Description STM32F103xC, STM32F103xD, STM32F103xE 22/123 Doc ID 14611 Rev 7 2.3.24 Universal serial bus (USB) The STM32F103xC, STM32F103xD and STM32F103xE performance line embed a USB device peripheral compatible with the USB full-speed 12 Mbs. The USB interface implements a full-speed (12 Mbit/s) function interface. It has software-configurable endpoint setting and suspend/resume support. The dedicated 48 MHz clock is generated from the internal main PLL (the clock source must use a HSE crystal oscillator). 2.3.25 GPIOs (general-purpose inputs/outputs) Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as input (with or without pull-up or pull-down) or as peripheral alternate function. Most of the GPIO pins are shared with digital or analog alternate functions. All GPIOs are high currentcapable except for analog inputs. The I/Os alternate function configuration can be locked if needed following a specific sequence in order to avoid spurious writing to the I/Os registers. I/Os on APB2 with up to 18 MHz toggling speed 2.3.26 ADC (analog to digital converter) Three 12-bit analog-to-digital converters are embedded into STM32F103xC, STM32F103xD and STM32F103xE performance line devices and each ADC shares up to 21 external channels, performing conversions in single-shot or scan modes. In scan mode, automatic conversion is performed on a selected group of analog inputs. Additional logic functions embedded in the ADC interface allow: ● Simultaneous sample and hold ● Interleaved sample and hold ● Single shunt The ADC can be served by the DMA controller. An analog watchdog feature allows very precise monitoring of the converted voltage of one, some or all selected channels. An interrupt is generated when the converted voltage is outside the programmed thresholds. The events generated by the general-purpose timers (TIMx) and the advanced-control timers (TIM1 and TIM8) can be internally connected to the ADC start trigger and injection trigger, respectively, to allow the application to synchronize A/D conversion and timers. 2.3.27 DAC (digital-to-analog converter) The two 12-bit buffered DAC channels can be used to convert two digital signals into two analog voltage signal outputs. The chosen design structure is composed of integrated resistor strings and an amplifier in inverting configuration
STM32F103xC,STM32F103xD,STM32F103xEDescriptionThis dualdigital Interfacesupportsthefollowingfeatures:.twoDACconverters:oneforeachoutputchannel.8-bitor12-bitmonotonicoutput.left or right data alignment in 12-bit mode.synchronizedupdate capability.noise-wave generation.triangular-wave generation.dual DACchannel independentorsimultaneous conversions.DMAcapabilityforeachchannel.externaltriggersforconversion.input voltage reference VREF+Eight DAC trigger inputs areused in the STM32F103xC,STM32F103xDandSTM32F103xEperformancelinefamily.TheDACchannelsaretriggeredthroughthetimerupdateoutputs that are alsoconnectedtodifferentDMAchannels.2.3.28TemperaturesensorThetemperaturesensorhastogenerateavoltagethatvarieslinearlywithtemperature.Theconversion range is between 2 V<VpDA <3.6 V. The temperature sensor is internallyconnectedtotheADC1_iN16inputchannelwhichisusedtoconvertthesensoroutputvoltage intoa digital value.2.3.29SerialwireJTAG debugport (SWJ-DP)The ARM SWJ-DP Interface is embedded, and is a combined JTAG and serial wire debugportthat enables either a serial wire debug or a JTAG probe to be connected to the target.TheJTAGTMSandTCKpinsaresharedrespectivelywithSWDIOandSWCLKandaspecific sequenceontheTMSpin isusedtoswitchbetweenJTAG-DPandSW-DP.EmbeddedTraceMacrocellTM2.3.30The ARM Embedded Trace Macrocell provides a greater visibility of the instruction anddataflowinsidethecPUcorebystreamingcompresseddataataveryhighratefromtheSTM32F10xxxthroughasmallnumberofETMpinstoanexternalhardwaretraceportanalyzer(TPA)device.TheTPAisconnectedtoahostcomputerusingUSB,Ethernet,orany other high-speed channel.Real-time instruction and data flow activity can be recordedandthenformattedfordisplayonthehostcomputerrunningdebuggersoftware.TPAhardwareiscommerciallyavailablefromcommondevelopmenttoolvendors.Itoperateswith third party debugger softwaretools.A23/123Doc ID14611Rev7
STM32F103xC, STM32F103xD, STM32F103xE Description Doc ID 14611 Rev 7 23/123 This dual digital Interface supports the following features: ● two DAC converters: one for each output channel ● 8-bit or 12-bit monotonic output ● left or right data alignment in 12-bit mode ● synchronized update capability ● noise-wave generation ● triangular-wave generation ● dual DAC channel independent or simultaneous conversions ● DMA capability for each channel ● external triggers for conversion ● input voltage reference VREF+ Eight DAC trigger inputs are used in the STM32F103xC, STM32F103xD and STM32F103xE performance line family. The DAC channels are triggered through the timer update outputs that are also connected to different DMA channels. 2.3.28 Temperature sensor The temperature sensor has to generate a voltage that varies linearly with temperature. The conversion range is between 2 V < VDDA < 3.6 V. The temperature sensor is internally connected to the ADC1_IN16 input channel which is used to convert the sensor output voltage into a digital value. 2.3.29 Serial wire JTAG debug port (SWJ-DP) The ARM SWJ-DP Interface is embedded, and is a combined JTAG and serial wire debug port that enables either a serial wire debug or a JTAG probe to be connected to the target. The JTAG TMS and TCK pins are shared respectively with SWDIO and SWCLK and a specific sequence on the TMS pin is used to switch between JTAG-DP and SW-DP. 2.3.30 Embedded Trace Macrocell™ The ARM® Embedded Trace Macrocell provides a greater visibility of the instruction and data flow inside the CPU core by streaming compressed data at a very high rate from the STM32F10xxx through a small number of ETM pins to an external hardware trace port analyzer (TPA) device. The TPA is connected to a host computer using USB, Ethernet, or any other high-speed channel. Real-time instruction and data flow activity can be recorded and then formatted for display on the host computer running debugger software. TPA hardware is commercially available from common development tool vendors. It operates with third party debugger software tools
PinoutsandpindescriptionsSTM32F103xC,STM32F103xD.STM32F103xE3Pinouts andpin descriptionsFigure 3.STM32F103xCandSTM32F103xEperformance lineBGA144ballout34561829101112PC13-()(O:(PDA(PED)(PoD)(PE2)PA14PA13PE3JTMSPER-RTCJTCKPC14()(po)(rai)(eere)(ps)(o)ipcPE4PC10d6c32jnPCIS:(PD4)(PFO(F)PG14(P)PB6(PG11)(pC12;VBATBOOTODDPG132SSWss-VDD_SVD.7VDD-ivss.8ivss.2PF10PF8Vss.PC3Vss_6VsS_7Vss_1PE11PD11C2760:PC4PE10PA4PG1 PE12PD10VssAWHPG4PC5)(PF13)PGOPE9PE13;PD13APA5PD9PD1(PBO)(eF12)(PF15)(PEO(PDB)PAD(PE14)(PD12:PB14PA215PB1(PF14(PB10)(PF11PE7PE15PB11PB12;DAl1479824/123DocID14611Rev7
Pinouts and pin descriptions STM32F103xC, STM32F103xD, STM32F103xE 24/123 Doc ID 14611 Rev 7 3 Pinouts and pin descriptions Figure 3. STM32F103xC and STM32F103xE performance line BGA144 ballout AI14798b VDD_7 PC2 PC3 PF6 PF8 VSS_4 VDD_6 H VDD_1 D PG13 PG14 PE5 PE6 C PG10 PG11 VDD_5 PB8 NRST B PG15 PG12 PC15- OSC32_OUT PB9 A 1 2 3 4 5 6 7 8 VBAT OSC_IN OSC_OUT VSS_5 G F E PF7 PC0 PF0 PF1 PF2 PF3 PF4 VSS VSS_10 PG9 PF5 _3 VDD_4 VDD_3 VDD_8 VSS_8 PE4 PB5 PB6 BOOT0 PB7 VSS_11 PF10 PC1 VDD_11 VDD_10 PF9 9 10 K J VSS_2 PD3 PD4 PD1 PC12 PD5 PC11 PD2 PD0 VDD_9 VSS_9 VDD_2 PG1 PA5 PC5 PE9 PB2/ BOOT1 PA4 PC4 PE10 VREF– PF13 PG0 VSSA PE12 PA1 PE13 PA0-WKUP PD9 PD10 PG4 PD13 11 12 PG8 PA10 NC PA9 PA11 PC10 PA12 PC9 PA8 PC7 PC6 PC8 PD14 PG3 PG2 PD15 M L PF15 PA7 PB1 PE7 PA6 PB0 PF12 PE8 VDDA PF11 PF14 VREF+ PE14 PA3 PE15 PA2 PB10 PD8 PD12 PB11 PB12 PB14 PB15 PB13 PC13- TAMPER-RTC PE3 PE2 PE1 PE0 PB4 JTRST PB3 JTDO PD6 PD7 PA15 JTDI PA14 JTCK PA13 JTMS VSS PE11 _6 VSS_7 VSS_1 PD11 PG7 PG6 PG5 PC14- OSC32_IN
STM32F103xC,STM32F103xD,STM32F103xEPinoutsandpindescriptionsFigure4.STM32F103xCandSTM32F103xElineBGA1ooballoutperformance2345678910T(PA1D)PC14-PC13- PB9 : PB7( PB4 )PB3)PA14;PE2PA13S32TAMPER,RTC....,PCi5-,((pBo)(PS)()(ecni)()(Pc10;PiVBAT:PA12OSC32_OoUI.....1.....(CE)(PBs )(po)(po)(PC12;OOSc_INVSS.5:PA9 ;PA11-福:BooTo(PES)(PEO)(PD4DPD7 ;: PDo :OSC_OUTVODLS:PA8PA10...EPE6NRSTPC2PD1 ;:PC9iVss_4'iVss_3'PC7;Vss_2VsS_1PC3NCVDD_4VDD_3PCOPCTPC8PCeGPB2PAO-WKUPPA4PC4PE10PB15HVREFEPB1DACSPA2PA6PBOPE8PE12PB10PB132VREF+PD9PD13YPB12:VDDAPAPA7PB1PE9PE13B11PD8PD12Al14601cST25/123Doc ID14611Rev7
STM32F103xC, STM32F103xD, STM32F103xE Pinouts and pin descriptions Doc ID 14611 Rev 7 25/123 Figure 4. STM32F103xC and STM32F103xE performance line BGA100 ballout AI14601c PE10 PC14- OSC32_IN PA5 PC5 PC3 PB4 PE15 PA4 PC4 PB2 H PE14 PE7 PE11 D PD4 PD3 PE3 PB8 C PD0 PC12 PE5 PB5 PC0 PE2 B PD2 PC11 PC15- OSC32_OUT PB7 PB6 A 1 2 3 4 5 6 7 8 OSC_IN VSS_5 OSC_OUT VDD_5 G F E PC1 VREF– PC13- TAMPER-RTC PB9 PB3 PA15 PE4 PE1 PE0 NRST PC2 PE6 VSS VSS_1 PD1 VSS_4 _3 VDD_4 VDD_3 NC PB15 VBAT PD5 PD6 BOOT0 PD7 VSS_2 VSSA PA1 VDD_2 VDD_1 PB14 PA0-WKUP 9 10 K J PD10 PD11 PA8 PA9 PA10 PA11 PC10 PA12 PA14 PA13 PC9 PC7 PC6 PD15 PC8 PD14 PE12 PA7 PB1 PB11 PA6 PB0 PE8 PB10 VDDA PE9 PE13 VREF+ PB13 PA3 PB12 PA2 PD8 PD9 PD13 PD12