PM0056Slife.augmentedProgramming manualSTM32F10xxx/20xxx/21xxx/L1xxxxCortex-M3 programming manualIntroductionThis programming manual provides information for application and system-level softwaredevelopers.ItgivesafulldescriptionoftheSTM32F10xxx/20xxx/21xxx/L1xxxxCortex-M3processorprogrammingmodel,instructionsetandcoreperipheralsTheSTM32F10xxx/20xxx/21xxx/L1xxxxCortex-M3processorisahighperformance32-bitprocessordesignedforthemicrocontrollermarket.Itoffers significantbenefitstodevelopers, including:Outstanding processing performancecombinedwitha fast interrupt handling·5.Enhanced system debugwithextensivebreakpointandtracecapabilitiesEfficientprocessorcore,systemandmemoriesUitra-low-powerconsumptionwithintegratedsleepmodes.Platformsecurity1/156December2017DocID15491Rev6www.st.com
December 2017 DocID15491 Rev 6 1/156 1 PM0056 Programming manual STM32F10xxx/20xxx/21xxx/L1xxxx Cortex®-M3 programming manual Introduction This programming manual provides information for application and system-level software developers. It gives a full description of the STM32F10xxx/20xxx/21xxx/L1xxxx Cortex®-M3 processor programming model, instruction set and core peripherals. The STM32F10xxx/20xxx/21xxx/L1xxxx Cortex®-M3 processor is a high performance 32-bit processor designed for the microcontroller market. It offers significant benefits to developers, including: • Outstanding processing performance combined with a fast interrupt handling • Enhanced system debug with extensive breakpoint and trace capabilities • Efficient processor core, system and memories • Ultra-low-power consumption with integrated sleep modes • Platform security www.st.com
PM0056ContentsContents1About this document101.110Typographicalconventions1.210Listofabbreviationsforregisters1.310AbouttheSTM32Cortex-M3processorandcoreperipherals.111.3.1System level interface121.3.2Integratedconfigurabledebug1.3.3Cortex-M3 processor features and benefits summary..121.3.4Cortex-M3 core peripherals.122The Cortex-M3 processor132.113Programmers model2.1.1.13Processormode and privilege levelsfor software execution2.1.2..13Stacks2.1.3..14Coreregisters2.1.4Exceptionsand interrupts.222.1.5Datatypes.222.1.6The Cortex microcontroller software interface standard (CMSiS) ....232.2Memory model.242.2.1Memory regions, types and attributes.252.2.2Memorysystemorderingofmemoryaccesses.252.2.3.26Behavior ofmemoryaccesses2.2.4.26Softwareorderingofmemoryaccesses2.2.5.27Bit-banding2.2.6..29Memoryendianness2.2.7..30Synchronization primitives2.2.8.31Programminghintsforthesynchronizationprimitives2.3·32Exceptionmodel2.3.1..32Exceptionstates2.3.2.32Exceptiontypes2.3.3Exception handlers.342.3.4Vectortable..352.3.5.35Exception priorities2.3.6.36Interruptprioritygrouping2.3.7Exception entry and return.37A2/156DocID15491Rev6
Contents PM0056 2/156 DocID15491 Rev 6 Contents 1 About this document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 1.1 Typographical conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 1.2 List of abbreviations for registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 1.3 About the STM32 Cortex®-M3 processor and core peripherals . . . . . . . . 10 1.3.1 System level interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 1.3.2 Integrated configurable debug . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 1.3.3 Cortex®-M3 processor features and benefits summary . . . . . . . . . . . . . 12 1.3.4 Cortex®-M3 core peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2 The Cortex®-M3 processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.1 Programmers model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.1.1 Processor mode and privilege levels for software execution . . . . . . . . . 13 2.1.2 Stacks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.1.3 Core registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.1.4 Exceptions and interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 2.1.5 Data types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 2.1.6 The Cortex® microcontroller software interface standard (CMSIS) . . . . 23 2.2 Memory model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 2.2.1 Memory regions, types and attributes . . . . . . . . . . . . . . . . . . . . . . . . . . 25 2.2.2 Memory system ordering of memory accesses . . . . . . . . . . . . . . . . . . . 25 2.2.3 Behavior of memory accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 2.2.4 Software ordering of memory accesses . . . . . . . . . . . . . . . . . . . . . . . . 26 2.2.5 Bit-banding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 2.2.6 Memory endianness . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 2.2.7 Synchronization primitives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 2.2.8 Programming hints for the synchronization primitives . . . . . . . . . . . . . . 31 2.3 Exception model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 2.3.1 Exception states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 2.3.2 Exception types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 2.3.3 Exception handlers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 2.3.4 Vector table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 2.3.5 Exception priorities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 2.3.6 Interrupt priority grouping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 2.3.7 Exception entry and return . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
PM0056Contents2.4Fault handling392.4.1.39Faulttypes2.4.2...40Fault escalation and hard faults2.4.3Fault status registers and fault address registers.412.4.4.41Lockup.2.541Power management2.5.1Enteringsleepmode..422.5.2.42Wakeupfromsleepmode2.5.3.43Theexternal event input2.5.4Power management programming hints.433The Cortex-M3 instruction set443.144Instructionsetsummary3.249Intrinsic functions3.350About the instruction descriptions3.3.1.50Operands3.3.2.51RestrictionswhenusingPCorSP3.3.3..51Flexible second operand3.3.4.52Shift operations3.3.5.55Addressalignment3.3.6.56PC-relativeexpressions3.3.7Conditional execution.563.3.8.58Instructionwidthselection3.4Memory access instructions593.4.1..60ADR3.4.2LDRandSTR,immediateoffset.613.4.3.63LDRandSTR,registeroffset3.4.4..64LDR and STR, unprivileged3.4.5..65LDR, PC-relative3.4.6LDMandSTM...673.4.7..68PUSHandPOP3.4.8LDREX and STREX.703.4.9CLREX.713.572General data processing instructions3.5.1ADD,ADC,SUB,SBC,andRSB.733.5.2AND,ORR,EOR,BIC,andORN.75A3/156DocID15491Rev6
DocID15491 Rev 6 3/156 PM0056 Contents 6 2.4 Fault handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 2.4.1 Fault types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 2.4.2 Fault escalation and hard faults . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 2.4.3 Fault status registers and fault address registers . . . . . . . . . . . . . . . . . 41 2.4.4 Lockup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 2.5 Power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 2.5.1 Entering sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 2.5.2 Wakeup from sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 2.5.3 The external event input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 2.5.4 Power management programming hints . . . . . . . . . . . . . . . . . . . . . . . . 43 3 The Cortex®-M3 instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 3.1 Instruction set summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 3.2 Intrinsic functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 3.3 About the instruction descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 3.3.1 Operands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 3.3.2 Restrictions when using PC or SP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 3.3.3 Flexible second operand . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 3.3.4 Shift operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 3.3.5 Address alignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 3.3.6 PC-relative expressions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 3.3.7 Conditional execution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 3.3.8 Instruction width selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 3.4 Memory access instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 3.4.1 ADR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 3.4.2 LDR and STR, immediate offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 3.4.3 LDR and STR, register offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 3.4.4 LDR and STR, unprivileged . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 3.4.5 LDR, PC-relative . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 3.4.6 LDM and STM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 3.4.7 PUSH and POP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 3.4.8 LDREX and STREX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 3.4.9 CLREX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 3.5 General data processing instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 3.5.1 ADD, ADC, SUB, SBC, and RSB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 3.5.2 AND, ORR, EOR, BIC, and ORN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
PM0056Contents763.5.3ASR,LSL, LSR, ROR,and RRX3.5.4CLZ773.5.5CMPandCMN...783.5.6MOV and MVN.793.5.7MOVT.803.5.8.81REV, REV16, REVSH, and RBIT3.5.9.82TSTandTEQ3.683Multiply and divide instructions3.6.1...83MUL, MLA, and MLS3.6.2UMULL, UMLAL, SMULL,and SMLAL.853.6.3SDIVandUDIV.863.7 87Saturating instructions3.7.1SSAT and USAT.873.8Bitfield instructions883.8.1.89BFC and BFI3.8.2SBFX and UBFX..893.8.3.90SXT and UXT3.8.4.91Branch and control instructions3.8.5B, BL, BX, and BLX..923.8.6CBZand CBNZ..933.8.7IT.943.8.8.96TBB and TBH3.997Miscellaneous instructions3.9.1BKPT..983.9.2CPS..983.9.3DMB.993.9.4DSB.1003.9.5ISB ..1003.9.6MRS1003.9.7MSR1013.9.8NOP.1023.9.9SEV.1023.9.10SVC1033.9.11WFE.1033.9.12WFI1044105Core peripheralsA4/156DocID15491Rev6
Contents PM0056 4/156 DocID15491 Rev 6 3.5.3 ASR, LSL, LSR, ROR, and RRX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 3.5.4 CLZ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 3.5.5 CMP and CMN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 3.5.6 MOV and MVN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 3.5.7 MOVT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 3.5.8 REV, REV16, REVSH, and RBIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 3.5.9 TST and TEQ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 3.6 Multiply and divide instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 3.6.1 MUL, MLA, and MLS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 3.6.2 UMULL, UMLAL, SMULL, and SMLAL . . . . . . . . . . . . . . . . . . . . . . . . . 85 3.6.3 SDIV and UDIV . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 3.7 Saturating instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 3.7.1 SSAT and USAT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 3.8 Bitfield instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 3.8.1 BFC and BFI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 3.8.2 SBFX and UBFX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 3.8.3 SXT and UXT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 3.8.4 Branch and control instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 3.8.5 B, BL, BX, and BLX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 3.8.6 CBZ and CBNZ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 3.8.7 IT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 3.8.8 TBB and TBH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 3.9 Miscellaneous instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 3.9.1 BKPT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 3.9.2 CPS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 3.9.3 DMB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 3.9.4 DSB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 3.9.5 ISB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 3.9.6 MRS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 3.9.7 MSR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 3.9.8 NOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 3.9.9 SEV . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 3.9.10 SVC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 3.9.11 WFE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 3.9.12 WFI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 4 Core peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
PM0056Contents4.1105AbouttheSTM32coreperipherals4.2105Memory protection unit (MPU)4.2.1MPUaccesspermissionattributes..1064.2.2.108MPUmismatch4.2.3.108Updating an MPU region1104.2.4MPU design hints and tips4.2.5111MPU typeregister (MPU_TYPER)4.2.6.112MPUcontrolregister(MPUCR)4.2.7..113MPU region number register (MPU_RNR)4.2.8114MPUregion baseaddress register (MPU_RBAR)4.2.9.116MPUregion attribute and size register (MPU_RASR)4.3...118Nested vectored interrupt controller (NVIC)4.3.1The CMSIS mapping of the Cortex-M3NVIC registers.1194.3.2.120Interruptset-enablereqisters(NVICISERx).4.3.3..121Interrupt clear-enable registers (NVIC_ICERx).1224.3.4Interrupt set-pending registers (NVIC_ISPRx)4.3.5.123Interrupt clear-pending registers (NVIC_ICPRx)4.3.6.124Interruptactivebitregisters(NVICIABRx)4.3.7125Interrupt priority registers (NVIC_IPRx)4.3.8..126Software trigger interrupt register (NVIC_STIR)4.3.9126Level-sensitiveandpulseinterrupts..1274.3.10NVIC designhintsandtips.1284.3.11NVICregistermap4.4.129System control block (SCB)4.4.1..129Auxiliarycontrolregister (SCB_ACTLR)4.4.2.130CPUIDbaseregister(SCB_CPUID)4.4.3Interrupt control and state register (SCB_ICSR)1314.4.4.133Vectortableoffsetregister(SCB_VTOR)4.4.5Application interrupt and reset control register (SCB_AIRCR).....1344.4.6.136Systemcontrol register(SCB_SCR)4.4.7.137Configuration and control register (SCB_CCR)4.4.8..138System handler priority registers (SHPRx)4.4.9.140Systemhandlercontrolandstateregister(SCB_SHCSR)4.4.10..142Configurablefaultstatusregister(SCBCFSR)4.4.11Hard fault status register (SCB_HFSR).1454.4.12Memory management fault address register (SCB_MMFAR)..1474.4.13Bus fault address register (SCB_BFAR).147A5/156DocID15491Rev6
DocID15491 Rev 6 5/156 PM0056 Contents 6 4.1 About the STM32 core peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 4.2 Memory protection unit (MPU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 4.2.1 MPU access permission attributes . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 4.2.2 MPU mismatch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 4.2.3 Updating an MPU region . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 4.2.4 MPU design hints and tips . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 4.2.5 MPU type register (MPU_TYPER) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 4.2.6 MPU control register (MPU_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 4.2.7 MPU region number register (MPU_RNR) . . . . . . . . . . . . . . . . . . . . . 113 4.2.8 MPU region base address register (MPU_RBAR) . . . . . . . . . . . . . . . . 114 4.2.9 MPU region attribute and size register (MPU_RASR) . . . . . . . . . . . . . 116 4.3 Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . . . .118 4.3.1 The CMSIS mapping of the Cortex®-M3 NVIC registers . . . . . . . . . . . 119 4.3.2 Interrupt set-enable registers (NVIC_ISERx) . . . . . . . . . . . . . . . . . . . . 120 4.3.3 Interrupt clear-enable registers (NVIC_ICERx) . . . . . . . . . . . . . . . . . . 121 4.3.4 Interrupt set-pending registers (NVIC_ISPRx) . . . . . . . . . . . . . . . . . . . 122 4.3.5 Interrupt clear-pending registers (NVIC_ICPRx) . . . . . . . . . . . . . . . . . 123 4.3.6 Interrupt active bit registers (NVIC_IABRx) . . . . . . . . . . . . . . . . . . . . . 124 4.3.7 Interrupt priority registers (NVIC_IPRx) . . . . . . . . . . . . . . . . . . . . . . . . 125 4.3.8 Software trigger interrupt register (NVIC_STIR) . . . . . . . . . . . . . . . . . 126 4.3.9 Level-sensitive and pulse interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . 126 4.3.10 NVIC design hints and tips . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 4.3.11 NVIC register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 4.4 System control block (SCB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 4.4.1 Auxiliary control register (SCB_ACTLR) . . . . . . . . . . . . . . . . . . . . . . . 129 4.4.2 CPUID base register (SCB_CPUID) . . . . . . . . . . . . . . . . . . . . . . . . . . 130 4.4.3 Interrupt control and state register (SCB_ICSR) . . . . . . . . . . . . . . . . . 131 4.4.4 Vector table offset register (SCB_VTOR) . . . . . . . . . . . . . . . . . . . . . . 133 4.4.5 Application interrupt and reset control register (SCB_AIRCR) . . . . . . 134 4.4.6 System control register (SCB_SCR) . . . . . . . . . . . . . . . . . . . . . . . . . . 136 4.4.7 Configuration and control register (SCB_CCR) . . . . . . . . . . . . . . . . . . 137 4.4.8 System handler priority registers (SHPRx) . . . . . . . . . . . . . . . . . . . . . 138 4.4.9 System handler control and state register (SCB_SHCSR) . . . . . . . . . 140 4.4.10 Configurable fault status register (SCB_CFSR) . . . . . . . . . . . . . . . . . 142 4.4.11 Hard fault status register (SCB_HFSR) . . . . . . . . . . . . . . . . . . . . . . . . 145 4.4.12 Memory management fault address register (SCB_MMFAR) . . . . . . . 147 4.4.13 Bus fault address register (SCB_BFAR) . . . . . . . . . . . . . . . . . . . . . . . 147