STM32F103xC,STM32F103xD,STM32F103xEDescription2.1DeviceoverviewTable 2.STM32F103xC,STM32F103xDandSTM32F103xEfeaturesandperipheralcountsPeripheralsSTM32F103RxSTM32F103VxSTM32F103ZxFlash memory in Kbytes25638451225638451225638451264(1)64 64 484848SRAM in KbytesYes(2)FSMCNoYes4General-purpose2TimersAdvanced-control2BasicSPI(I2s)(3)3(2)[Pc2USART5CommUSB11CAN1SDIO5180112GPIOS33312-bit ADC161621Number of channels2212-bit DACNumberofchannelsCPUfrequency72 MHz2.0 to 3.6 VOperatingvoltageAmbienttemperatures:-40to+85C/-40to+105°C(seeTable10)OperatingtemperaturesJunction temperature:-40 to+125C(see Table 10)PackageLQFP64WLCSP64LQFP100,BGA100LQFP144,BGA1441.64 KB RAM for 256 KB Flash are available on devices delivered in CSP packages only.2.FortheLQFP100andBGA100packages,onlyFSMC Bank1and Bank2 are available.Bank1can onlysupportamultiplexedNOR/PSRAMmemoryusingtheNE1ChipSelect.Bank2canonlysupporta16-or8-bitNANDFlashmemoryusingtheNCE2ChipSelect.Theinterrupt linecannotbeusedsincePortGisnot available in this package.3.The SPI2 and SPI3 interfaces give the flexibility to work in an exclusive way in either the SPImode or thej2s audio mode.SDoc ID14611Rev711/123
STM32F103xC, STM32F103xD, STM32F103xE Description Doc ID 14611 Rev 7 11/123 2.1 Device overview Table 2. STM32F103xC, STM32F103xD and STM32F103xE features and peripheral counts Peripherals STM32F103Rx STM32F103Vx STM32F103Zx Flash memory in Kbytes 256 384 512 256 384 512 256 384 512 SRAM in Kbytes 48 64(1) 1. 64 KB RAM for 256 KB Flash are available on devices delivered in CSP packages only. 48 64 48 64 FSMC No Yes(2) 2. For the LQFP100 and BGA100 packages, only FSMC Bank1 and Bank2 are available. Bank1 can only support a multiplexed NOR/PSRAM memory using the NE1 Chip Select. Bank2 can only support a 16- or 8-bit NAND Flash memory using the NCE2 Chip Select. The interrupt line cannot be used since Port G is not available in this package. Yes Timers General-purpose 4 Advanced-control 2 Basic 2 Comm SPI(I2S)(3) 3. The SPI2 and SPI3 interfaces give the flexibility to work in an exclusive way in either the SPI mode or the I 2S audio mode. 3(2) I 2C 2 USART 5 USB 1 CAN 1 SDIO 1 GPIOs 51 80 112 12-bit ADC Number of channels 3 16 3 16 3 21 12-bit DAC Number of channels 2 2 CPU frequency 72 MHz Operating voltage 2.0 to 3.6 V Operating temperatures Ambient temperatures: –40 to +85 °C /–40 to +105 °C (see Table 10) Junction temperature: –40 to + 125 °C (see Table 10) Package LQFP64 WLCSP64 LQFP100, BGA100 LQFP144, BGA144
DescriptionSTM32F103xC,STM32F103xD.STM32F103xEFigure 1.STM32F103xCSTM32F103xDandSTM32F103xEperformancelineblockdiagramTAGEBOS@VDDTPIUas ASTrace/trigTracePowerSWJTAGPhiVDDcontrollerNJTRSTVolt, regONSEVss1.3 VtobusFiash 512 Kbytes蓝意rasoCortex-M3 CPU64 biteVODASupplyDbusas AFFmax: 48/72 MHz[NRSTsupervisionAoRVDDAPOR PDRKaysterSRAMLVssAaVhnANVIC64 KBPVDIntsngRC 8 MHzGP DMA1@vnrA[25:0]RC 40 kHz[osc_IN7 channelsXTALOLOSc_OUT2Hy14-16 MHzGP DMA27IWDGaL★PCLK15 channelsReset&18RaeraceEROTClockVBAT=1.8Vto3.6VntroeHyOVBATFSMC-FCLKJoSC32_INNL (or NADV)XTAL32KabAFOSC32_OUTBadupTAMPER-RTC/ATGregALARM/SECOND OUTSDIO.interfaceBackupCKasAFAHB2AHB2TIM24channels, ETR as AFAPB2APB132WKUP112AFCTIM3 channels, ETR as L山PA[15:0] <TIM44 channels, ETR as AGPIO port A2OCATIM5>4 channels as AFPB[15:0] GPIO port B0zRXTX.CTS.RTS,-MPC[15:0] GPIO port CUSART2CKasAFPD[15:0] V国EXTXATTS,RTS,GPIO port D介USART3:taFPE[15:0] GPIOportE>RX,TXasAFUART4PF[15:0] RX,TXasAFGPIO porntFUARTSPG[15:0] GPIO port GMOSISD.MISOSPI2/12S2SCK/CK,MCK,NSSWS as AF4 channelsTIM1MOSI/SD,MISOSPI3/12S3BKIN,ETRas AFSCKICK,MCK,NSsWSasF4.channels.TIM8个I2C1SCL, SDA, SMBA as AFBKIN,ETR as AFL>DAMBasSPI1I2C2SRAM 512BNORINS AFbxCAN deviceWWDGUSART1RTS.TCKCTSAFUSBDP/CAN_TXUSB 2.0 FSTLUSBDM/CAN_RXdeviceTemp. sensorTIM6DAC_OUT1as AF8ADC123_INsS12-bit ADC1Fcommon to the3ADC+DAC_OUT2 a5 AFTIM7BADPIABCO12-bit ADC2IIF5 ADC3_INs on ADC312-bit ADC3|IFGVDDANREReVDDAREF+ai14666f4=-40°C to +85C (suffix 6, see Table 71)or-40°C to +105C (suffix 7,see Table71), junction temperature up to1.TA105C or 125°C, respectively.2.AF=alternatefunction on VOportpin.SA12/123DocID14611Rev7
Description STM32F103xC, STM32F103xD, STM32F103xE 12/123 Doc ID 14611 Rev 7 Figure 1. STM32F103xC, STM32F103xD and STM32F103xE performance line block diagram 1. TA = –40 °C to +85 °C (suffix 6, see Table 71) or –40 °C to +105 °C (suffix 7, see Table 71), junction temperature up to 105 °C or 125 °C, respectively. 2. AF = alternate function on I/O port pin. PA[15:0] EXT.IT 112AF AHB2 2x(8x16it) b WKUP Fmax: 48/72 MHz VSS I2C2 GP DMA1 TIM2 TIM3 XTAL32kHz Flash 512 Kbytes VDD Backup interface TIM4 Bus Matrix 64 bit RTC RC 8 MHz Cortex-M3 CPU Dbus obl Flash interface USART2 SPI2 / I2S2 Backup reg TIM1 I2C1 RX, TX, CTS, RTS, USART3 RC 40 kHz Standby IWDG @VBAT POR / PDR @VDDA VBAT=1.8 V to 3.6 V CK as AF RX, TX, CTS, RTS, CK as AF NVIC SPI1 interface @VDDA Int PVD APB2 AWU TIM8 2x(S8PI x16it)3 / I2 b S3 UART4 RX,TX as AF UART5 RX,TX as AF TIM5 PLL @VDDA FSMC DAC_OUT1 as AF DAC_OUT2 as AF SRAM 64 KB GP DMA2 TIM6 TIM7 NJTRST JTDI JTCK/SWCLK JTMS/SWDIO JTDO as AF A[25:0] D[15:0] CLK NOE NWE NE[4:1] NBL[1:0] NWAIT NL (or NADV) as AF 7 channels 5 channels GPIO port A GPIO port B GPIO port C GPIO port D GPIO port E GPIO port F GPIO port G USART1 Temp. sensor 12-bit ADC1 12-bit ADC2 12-bit ADC3 IF IF IF PB[15:0] PC[15:0] PD[15:0] PE[15:0] PF[15:0] PG[15:0] 4 channels 3 compl. channels BKIN, ETR as AF 4 channels 3 compl. channels BKIN, ETR as AF MOSI, MISO, SCK, NSS as AF RX, TX, CTS, RTS, CK as AF 8 ADC123_INs common to the 3 ADCs 8 ADC12_INs common to ADC1 & ADC2 5 ADC3_INs on ADC3 VREF+ VREF– @ VDDA APB2: Fmax = 48/72 MHz APB1 Trace controller Pbus Ibus System Reset & Clock control PCLK1 PCLK2 HCLK FCLK Power Volt. reg. 3.3 V to 1.8 V Supply supervision @VDD POR Reset NRST VDDA VSSA OSC_IN OSC_OUT @VDD XTAL OSC 4-16 MHz OSC32_IN OSC32_OUT TAMPER-RTC/ ALARM/SECOND OUT 4 channels, ETR as AF 4 channels, ETR as AF 4 channels, ETR as AF 4 channels as AF MOSI/SD, MISO SCK/CK, MCK, NSS/WS as AF MOSI/SD, MISO SCK/CK, MCK, NSS/WS as AF SCL, SDA, SMBA as AF SCL, SDA, SMBA as AF bxCAN device USB 2.0 FS device USBDP/CAN_TX USBDM/CAN_RX SRAM 512 B WWDG ai14666f APB1: Fmax = 24/36 MHz TRACECLK TRACED[0:3] as AS SW/JTAG TPIU Trace/trig SDIO D[7:0] CMD CK as AF AHB: Fmax = 48/72 MHz AHB2 IF 12bit DAC1 IF 12bit DAC 2
STM32F103xC,STM32F103xD,STM32F103xEDescriptionFigure 2.Clock treeUSBCLKUSB48 MHzPrescaler to USB interface/1,1.52S3CLKto 12S3Peripheral clock12S2CLKto I2S2Peripheral clockSDIOCLKto SDIOenaol8 MHzPeripheral clockHSIHSIRCenableFSMCCLK+toFSMCPerpheral clock [[2]enableHCLK72 MHz maxAHBbus.comemoryandDMAClockEnable (4'bins)★ to Cortex System timer/8SWPLLSRCPLLMULFCLKCortexftree running clockAPB1AHBx16SY$CLK36MHzmaxPCLK1PrescalerPrescalerx2, x3, x4LCLK72 MHZLtoAoR/1,2, 4, 8, 16/1,2.512PLLmayshealClock peripheralsPeriphHSEEnable(20 bits)IM2.3,4,5,6,7toTIM2,3.4.5.6and7if (APB1 prescaler =1) x1TIMXCLKelse xCSSeripheral ClockEnable (6 bits)APB2PLLXTPRE72 MHzmaxPCLK2Prescaler1OSC_OUTperipherals to APB2/1, 2, 4, 8, 164-16 MHZPeripheral ClockHSEOSCEnable (15 bits)OSC_INL12TIM1 & 8 timersto TIM1 and TIM8if (APB2 prescaler =1) x1TIMxCLKelse x2Peripheral Clock/128lEnable (2 bit)ADCto ADC1,2or 3OSC32_INto RTCPrescaleLSEOSCLSEADCCLK12, 4,6, 8RTCCLK32.768 kHzOSC32_OUTHCLK12,12RTCSEL[1:0]To SDIO AHB interfacePeripheral clockto Independent Watchdog (IWDG)LSIRCLSIenable40kHzIWDGCLKLegend:MainPLLCLKClock OutputHSE = High Speed External clock signalMCOHSIHSI = High Speed Internal clock signalHSELSI = Low Speed Intermal clock signalLSE = Low Speed Extermal clock signalSYSCLKMCOal14752b1.When the HSl is used as a PLL clock input, the maximum system clock frequency that can be achieved is64 MHz.2.For the USBfunction to be available,both HSE and PLL must be enabled, with the CPUrunning at either48 MHz or 72 MHz.3.TohaveanADCconversiontimeof1μs,APB2mustbeat14MHz,28MHzor56MHz.SDocID14611Rev713/123
STM32F103xC, STM32F103xD, STM32F103xE Description Doc ID 14611 Rev 7 13/123 Figure 2. Clock tree 1. When the HSI is used as a PLL clock input, the maximum system clock frequency that can be achieved is 64 MHz. 2. For the USB function to be available, both HSE and PLL must be enabled, with the CPU running at either 48 MHz or 72 MHz. 3. To have an ADC conversion time of 1 µs, APB2 must be at 14 MHz, 28 MHz or 56 MHz. HSE OSC 4-16 MHz OSC_IN OSC_OUT OSC32_IN OSC32_OUT LSE OSC 32.768 kHz HSI RC 8 MHz LSI RC 40 kHz to Independent Watchdog (IWDG) PLL x2, x3, x4 PLLMUL HSE = High Speed External clock signal LSE = Low Speed External clock signal LSI = Low Speed Internal clock signal HSI = High Speed Internal clock signal Legend: MCO Clock Output Main PLLXTPRE /2 ., x16 AHB Prescaler /1, 2.512 /2 PLLCLK HSI HSE APB1 Prescaler /1, 2, 4, 8, 16 ADC Prescaler /2, 4, 6, 8 ADCCLK PCLK1 HCLK PLLCLK to AHB bus, core, memory and DMA USBCLK to USB interface USB Prescaler /1, 1.5 to ADC1, 2 or 3 LSE LSI HSI /128 /2 HSI HSE peripherals to APB1 Peripheral Clock Enable (20 bits) Enable (6 bits) Peripheral Clock APB2 Prescaler /1, 2, 4, 8, 16 PCLK2 TIM1 & 8 timers to TIM1 and TIM8 peripherals to APB2 Peripheral Clock Enable (15 bits) Enable (2 bit) Peripheral Clock 48 MHz 72 MHz max 72 MHz 72 MHz max 36 MHz max to RTC PLLSRC SW MCO CSS /8 to Cortex System timer Clock Enable (4 bits) SYSCLK max RTCCLK RTCSEL[1:0] TIMxCLK TIMXCLK IWDGCLK SYSCLK FCLK Cortex free running clock /2 TIM2,3,4,5,6,7 to TIM2,3,4,5,6 and 7 To SDIO AHB interface Peripheral clock enable HCLK/2 to FSMC FSMCCLK to SDIO Peripheral clock enable Peripheral clock enable to I2S3 to I2S2 Peripheral clock enable Peripheral clock enable I2S3CLK I2S2CLK SDIOCLK ai14752b If (APB1 prescaler =1) x1 else x2 If (APB2 prescaler =1) x1 else x2
DescriptionSTM32F103xC.STM32F103xD.STM32F103xE2.2Full compatibilitythroughoutthefamilyTheSTM32F103xxisacompletefamilywhosemembersarefullypin-to-pin,softwareandfeaturecompatible.Inthereferencemanual,theSTM32F103x4andSTM32F103x6areidentifiedaslow-densitydevices,theSTM32F103x8andSTM32F103xBarereferredtoasmedium-densitydevicesandtheSTM32F103xC,STM32F103xDandSTM32F103xEarereferredtoashigh-densitydevicesLow-densityandhigh-densitydevicesareanextensionoftheSTM32F103x8/Bmedium-densitydevices,theyarespecifiedintheSTM32F103x4/6andSTM32F103xC/D/Edatasheets,respectively.Low-densitydevicesfeaturelowerFlashmemoryandRAMcapacities, less timers and peripherals.High-density devices have higher Flash memoryandRAMcapacities,andadditionalperipheralslikeSDIO,FSMC,2andDACwhileremainingfullycompatiblewiththeothermembersofthefamilyTheSTM32F103x4,STM32F103x6,STM32F103xC,STM32F103xDandSTM32F103xEareadrop-inreplacementfortheSTM32F103x8/Bdevices,allowingtheusertotrydifferentmemorydensitiesandprovidingagreaterdegreeoffreedomduringthedevelopmentcycle.Moreover,the STM32F103xx performanceline family isfully compatible with all existingSTM32F101xxaccesslineandSTM32F102xxUSBaccesslinedevicesTable 3.STM32F103xxfamilyMedium-densitydevicesLow-densitydevicesHigh-density devices512 KB16 KB32 KB64 KB128 KB256 KB384KBFlash(1)FlashFlashFlashFlashFlashFlashPinout48or64 KB(2)6KB RAM10KBRAM20KBRAM20KBRAM64KBRAM64KBRAMRAM1445×USARTs4×16-bit timers,2×basic timers1003×USARTs3×SPls2×/2Ss2×12CsUSB,CAN,2×PWMtimers3×16-bit timers2×USARTs642×SPIs,2×/Cs,USB3×ADCs,2×DACs,1×SDIO2×16-bit timersFSMC (100-and 144-pin packages(3)CAN,1×PWMtimer1 × SPI, 1 ×12C,USB,2×ADCs48CAN,1×PWMtimer2×ADCs36For orderable part numbers that do not show the A internal code after the temperature range code (6 or 7),Ithe reference datasheet for electrical characteristics is that of the STM32F103x8/B medium-densitydevices264KBRAMfor 256KBFlash are available on devices delivered in CSPpackages only.3. Ports F and G are not available in devices delivered in 100-pin packages.SA14/123Doc ID14611Rev7
Description STM32F103xC, STM32F103xD, STM32F103xE 14/123 Doc ID 14611 Rev 7 2.2 Full compatibility throughout the family The STM32F103xx is a complete family whose members are fully pin-to-pin, software and feature compatible. In the reference manual, the STM32F103x4 and STM32F103x6 are identified as low-density devices, the STM32F103x8 and STM32F103xB are referred to as medium-density devices and the STM32F103xC, STM32F103xD and STM32F103xE are referred to as high-density devices. Low-density and high-density devices are an extension of the STM32F103x8/B mediumdensity devices, they are specified in the STM32F103x4/6 and STM32F103xC/D/E datasheets, respectively. Low-density devices feature lower Flash memory and RAM capacities, less timers and peripherals. High-density devices have higher Flash memory and RAM capacities, and additional peripherals like SDIO, FSMC, I2S and DAC while remaining fully compatible with the other members of the family. The STM32F103x4, STM32F103x6, STM32F103xC, STM32F103xD and STM32F103xE are a drop-in replacement for the STM32F103x8/B devices, allowing the user to try different memory densities and providing a greater degree of freedom during the development cycle. Moreover, the STM32F103xx performance line family is fully compatible with all existing STM32F101xx access line and STM32F102xx USB access line devices. Table 3. STM32F103xx family Pinout Low-density devices Medium-density devices High-density devices 16 KB Flash 32 KB Flash(1) 1. For orderable part numbers that do not show the A internal code after the temperature range code (6 or 7), the reference datasheet for electrical characteristics is that of the STM32F103x8/B medium-density devices. 64 KB Flash 128 KB Flash 256 KB Flash 384 KB Flash 512 KB Flash 6 KB RAM 10 KB RAM 20 KB RAM 20 KB RAM 48 or 64 KB(2) RAM 2. 64 KB RAM for 256 KB Flash are available on devices delivered in CSP packages only. 64 KB RAM 64 KB RAM 144 5 × USARTs 4 × 16-bit timers, 2 × basic timers 3 × SPIs, 2 × I2Ss, 2 × I2Cs USB, CAN, 2 × PWM timers 3 × ADCs, 2 × DACs, 1 × SDIO FSMC (100- and 144-pin packages(3)) 3. Ports F and G are not available in devices delivered in 100-pin packages. 100 3 × USARTs 3 × 16-bit timers 2 × SPIs, 2 × I2Cs, USB, CAN, 1 × PWM timer 2 × ADCs 64 2 × USARTs 2 × 16-bit timers 1 × SPI, 1 × I2C, USB, CAN, 1 × PWM timer 2 × ADCs 48 36
STM32F103xC,STM32F103xD,STM32F103xEDescription2.3Overview2.3.1ARM?CortexTM-M3corewithembeddedFlashandSRAMTheARMCortexTm-M3processoristhelatestgenerationofARMprocessorsforembeddedsystems.Ithasbeendevelopedtoprovidealow-costplatformthatmeetstheneedsofMCUimplementation,withareducedpin countandlow-powerconsumption,whiledeliveringoutstandingcomputationalperformanceandanadvancedsystemresponsetointerrupts.The ARM CortexTM-M3 32-bit RISC processor features exceptional code-efficiency,deliveringthe high-performanceexpectedfromanARM core inthememorysizeusuallyassociated with8-and 16-bit devices.WithitsembeddedARMcore,STM32F103xCSTM32F103xDandSTM32F103xEperformance linefamily is compatiblewithall ARMtools and software.Figure1showsthegeneralblockdiagramofthedevicefamily.2.3.2EmbeddedFlashmemoryUp to 512 Kbytes of embedded Flash is available for storing programs and data.2.3.3CRC(cyclicredundancycheck)calculationunitTheCRC(cyclicredundancycheck)calculationunit isusedtogetaCRCcodefroma32-bitdata word and a fixed generator polynomial.Amongotherapplications,CRC-basedtechniquesareusedtoverifydatatransmissionorstorage integrity.In the scopeofthe EN/IEC60335-1standard,they offera meansofverifyingtheFlashmemory integrity.TheCRCcalculationunit helps computea signatureofthe software during runtime, to be compared with a reference signature generated at link-time and stored at a givenmemorylocation.2.3.4EmbeddedSRAMUpto64KbytesofembeddedSRAMaccessed(read/write)atCPUclockspeedwith0waitstates.2.3.5FSMC (flexible staticmemory controller)The FSMC is embedded in the STM32F103xC,STM32F103xD and STM32F103xEperformance linefamily.It has fourChip Select outputs supporting thefollowing modes:PCCard/CompactFlash,SRAM,PSRAM,NORandNAND.Functionality overview:The three FSMC interrupt lines are ORed in order to be connected to the NVIC..WriteFIFOCodeexecutionfromexternalmemoryexceptforNANDFlashandPCCard.The targeted frequency, fcLk, is HCLK/2, so external access is at 36 MHz when HCLK.is at 72MHz and external access is at 24 MHz when HCLK is at 48 MHzSTDocID14611Rev715/123
STM32F103xC, STM32F103xD, STM32F103xE Description Doc ID 14611 Rev 7 15/123 2.3 Overview 2.3.1 ARM® Cortex™-M3 core with embedded Flash and SRAM The ARM Cortex™-M3 processor is the latest generation of ARM processors for embedded systems. It has been developed to provide a low-cost platform that meets the needs of MCU implementation, with a reduced pin count and low-power consumption, while delivering outstanding computational performance and an advanced system response to interrupts. The ARM Cortex™-M3 32-bit RISC processor features exceptional code-efficiency, delivering the high-performance expected from an ARM core in the memory size usually associated with 8- and 16-bit devices. With its embedded ARM core, STM32F103xC, STM32F103xD and STM32F103xE performance line family is compatible with all ARM tools and software. Figure 1 shows the general block diagram of the device family. 2.3.2 Embedded Flash memory Up to 512 Kbytes of embedded Flash is available for storing programs and data. 2.3.3 CRC (cyclic redundancy check) calculation unit The CRC (cyclic redundancy check) calculation unit is used to get a CRC code from a 32-bit data word and a fixed generator polynomial. Among other applications, CRC-based techniques are used to verify data transmission or storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of verifying the Flash memory integrity. The CRC calculation unit helps compute a signature of the software during runtime, to be compared with a reference signature generated at linktime and stored at a given memory location. 2.3.4 Embedded SRAM Up to 64 Kbytes of embedded SRAM accessed (read/write) at CPU clock speed with 0 wait states. 2.3.5 FSMC (flexible static memory controller) The FSMC is embedded in the STM32F103xC, STM32F103xD and STM32F103xE performance line family. It has four Chip Select outputs supporting the following modes: PC Card/Compact Flash, SRAM, PSRAM, NOR and NAND. Functionality overview: ● The three FSMC interrupt lines are ORed in order to be connected to the NVIC ● Write FIFO ● Code execution from external memory except for NAND Flash and PC Card ● The targeted frequency, fCLK, is HCLK/2, so external access is at 36 MHz when HCLK is at 72 MHz and external access is at 24 MHz when HCLK is at 48 MHz