ListoftablesSTM32F103xC,STM32F103xD,STM32F103xE...82Table 45.1/Ostaticcharacteristics.....84Table 46.OutputvoltagecharacteristicsTable 47.O AC characteristics......85...86Table 48.NRSTpincharacteristicsTable 49.TIMx characteristics..87ccharacteristics.....88Table 50.Table 51.SCL frequency (fpCLK1= 36 MHz.,VDD = 3.3 V).89SPIcharacteristics....90Table 52.Table 53.scharacteristics..93Table 54.SD/MMCcharacteristics.96.96Table 55.USBstartuptime....97Table 56.USBDCelectrical characteristics.....Table 57.USB:full-speedelectricalcharacteristics.97..98Table 58.ADCcharacteristicsTable 59..99RAIN max for fADC = 14 MHz. . :..99Table 60.ADCaccuracy-limitedtestconditionsTable 61.ADCaccuracy100...103Table 62.DACcharacteristicsTable 63.TScharacteristics.105Table 64.LFBGA144-144-ball lowprofile finepitch ball grid array,10x10mm,.1070.8 mm pitch,packagedata..Table 65.LFBGA100-10x10mmlowprofile finepitchball grid arraypackage....108mechanicaldata.Table 66.WLCSP,64-ball4.466×4.395mm,0.500mmpitch,wafer-levelchip-scale....109packagemechanicaldata...Table 67.LQFP144,20x20mm,144-pinlow-profilequadflatpackagemechanicaldata111..Table 68.LQPF100 - 14 x 14 mm 100-pin low-profile quad flat package mechanical data. .. .... 112Table 69.LQFP64-10x10mm64pinlow-profilequadflatpackagemechanicaldata....113Table 70.Package thermalcharacteristics...114Table 71.Ordering information scheme........117S6/123Doc ID14611Rev7
List of tables STM32F103xC, STM32F103xD, STM32F103xE 6/123 Doc ID 14611 Rev 7 Table 45. I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 Table 46. Output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 Table 47. I/O AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 Table 48. NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 Table 49. TIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 Table 50. I2C characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 Table 51. SCL frequency (fPCLK1= 36 MHz.,VDD = 3.3 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 Table 52. SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 Table 53. I2S characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 Table 54. SD / MMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 Table 55. USB startup time. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 Table 56. USB DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 Table 57. USB: full-speed electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 Table 58. ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 Table 59. RAIN max for fADC = 14 MHz. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 Table 60. ADC accuracy - limited test conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 Table 61. ADC accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 Table 62. DAC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 Table 63. TS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 Table 64. LFBGA144 – 144-ball low profile fine pitch ball grid array, 10 x 10 mm, 0.8 mm pitch, package data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 Table 65. LFBGA100 - 10 x 10 mm low profile fine pitch ball grid array package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 Table 66. WLCSP, 64-ball 4.466 × 4.395 mm, 0.500 mm pitch, wafer-level chip-scale package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 Table 67. LQFP144, 20 x 20 mm, 144-pin low-profile quad flat package mechanical data . . . . . . . 111 Table 68. LQPF100 – 14 x 14 mm 100-pin low-profile quad flat package mechanical data. . . . . . . 112 Table 69. LQFP64 – 10 x 10 mm 64 pin low-profile quad flat package mechanical data. . . . . . . . . 113 Table 70. Package thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 Table 71. Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
STM32F103xC,STM32F103xD,STM32F103xEList of figuresList of figuresFigure 1.STM32F103xC,STM32F103xD and STM32F103xEperformance line block diagram..12Figure 2.Clocktree..13Figure3.STM32F103xCandSTM32F103xEperformancelineBGA144ballout.24...25Figure 4.STM32F103xCandSTM32F103xEperformancelineBGA100balloutFigure 5..26STM32F103xCandSTM32F103xEperformancelineLQFP144pinout..Figure 6....27STM32F103xCandSTM32F103xEperformancelineLQFP100pinout....Figure7.STM32F103xCandSTM32F103xEperformanceline.28LQFP64pinout.Figure 8.STM32F103xCandSTM32F103xEperformanceline.29WLCSP64ballout,ballside..38Figure 9.Memorymap....Figure10..39Pinloadingconditions.Figure 11..39Pin inputvoltage....40Figure 12.Powersupplyscheme.Figure 13..40CurrentconsumptionmeasurementschemeFigure 14.TypicalcurrentconsumptioninRunmodeversusfrequency(at3.6V).46codewithdataprocessingrunningfromRAM,peripheralsenabled.Figure15.TypicalcurrentconsumptioninRunmodeversusfrequency(at3.6V)codewithdataprocessingrunningfromRAM,peripheralsdisabled...46Figure 16.Typical current consumption on VBAT with RTC on vs. temperature at different VBAT....48values..Figure 17.Typicalcurrent consumption in Stop mode with regulatorin runmode.49versus temperature at different Vpp values ....Figure 18.TypicalcurrentconsumptioninStopmodewithregulatorinlow-power.49modeversus temperatureat different Vpp values.Figure 19.Typical currentconsumption inStandbymodeversustemperatureat.50differentVppvaluesFigure 20...55High-speedexternalclocksourceACtimingdiagram..56Figure 21.Low-speed external clock source AC timing diagram....57Figure 22.Typicalapplicationwithan8MHzcrystal.Figure23..58Typicalapplicationwitha32.768kHzcrystal.Figure 24..62Asynchronousnon-multiplexedSRAM/PSRAM/NORreadwaveforms.63Figure 25.Asynchronousnon-multiplexedSRAM/PSRAM/NORwritewaveformsFigure 26.Asynchronous multiplexed PSRAM/NOR read waveforms..64....65Figure 27.AsynchronousmultiplexedPSRAM/NORwritewaveforms.66Figure 28.SynchronousmultiplexedNOR/PSRAMreadtimings.68Figure 29.Synchronousmultiplexed PSRAM write timings.Figure 30.Synchronousnon-multiplexedNOR/PSRAMreadtimings..70Figure 31.Synchronousnon-multiplexedPSRAMwritetimings..71Figure 32.Pc Card/CompactFlash controller waveforms for common memory read access......72Figure 33.PCCard/CompactFlashcontrollerwaveformsforcommonmemorywriteaccess......73Figure 34.PCCard/CompactFlashcontrollerwaveformsforattributememory read.74access...Figure 35.PCCard/CompactFlashcontrollerwaveformsforattributememorywrite.75access..Figure 36.PCCard/CompactFlashcontrollerwaveformsforIVOspacereadaccess.75Figure 37.PC Card/CompactFlash controller waveforms for I/O space write access.:.76NANDcontrollerwaveformsforreadaccess..78Figure38.ST7/123DocID14611Rev7
STM32F103xC, STM32F103xD, STM32F103xE List of figures Doc ID 14611 Rev 7 7/123 List of figures Figure 1. STM32F103xC, STM32F103xD and STM32F103xE performance line block diagram . . . 12 Figure 2. Clock tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Figure 3. STM32F103xC and STM32F103xE performance line BGA144 ballout . . . . . . . . . . . . . . . 24 Figure 4. STM32F103xC and STM32F103xE performance line BGA100 ballout . . . . . . . . . . . . . . . 25 Figure 5. STM32F103xC and STM32F103xE performance line LQFP144 pinout. . . . . . . . . . . . . . . 26 Figure 6. STM32F103xC and STM32F103xE performance line LQFP100 pinout. . . . . . . . . . . . . . . 27 Figure 7. STM32F103xC and STM32F103xE performance line LQFP64 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Figure 8. STM32F103xC and STM32F103xE performance line WLCSP64 ballout, ball side . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Figure 9. Memory map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Figure 10. Pin loading conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Figure 11. Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Figure 12. Power supply scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Figure 13. Current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Figure 14. Typical current consumption in Run mode versus frequency (at 3.6 V) - code with data processing running from RAM, peripherals enabled. . . . . . . . . . . . . . . . . . 46 Figure 15. Typical current consumption in Run mode versus frequency (at 3.6 V) - code with data processing running from RAM, peripherals disabled . . . . . . . . . . . . . . . . . 46 Figure 16. Typical current consumption on VBAT with RTC on vs. temperature at different VBAT values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Figure 17. Typical current consumption in Stop mode with regulator in run mode versus temperature at different VDD values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Figure 18. Typical current consumption in Stop mode with regulator in low-power mode versus temperature at different VDD values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Figure 19. Typical current consumption in Standby mode versus temperature at different VDD values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Figure 20. High-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Figure 21. Low-speed external clock source AC timing diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Figure 22. Typical application with an 8 MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Figure 23. Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Figure 24. Asynchronous non-multiplexed SRAM/PSRAM/NOR read waveforms . . . . . . . . . . . . . . . 62 Figure 25. Asynchronous non-multiplexed SRAM/PSRAM/NOR write waveforms . . . . . . . . . . . . . . . 63 Figure 26. Asynchronous multiplexed PSRAM/NOR read waveforms. . . . . . . . . . . . . . . . . . . . . . . . . 64 Figure 27. Asynchronous multiplexed PSRAM/NOR write waveforms . . . . . . . . . . . . . . . . . . . . . . . . 65 Figure 28. Synchronous multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Figure 29. Synchronous multiplexed PSRAM write timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 Figure 30. Synchronous non-multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . 70 Figure 31. Synchronous non-multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Figure 32. PC Card/CompactFlash controller waveforms for common memory read access . . . . . . . 72 Figure 33. PC Card/CompactFlash controller waveforms for common memory write access. . . . . . . 73 Figure 34. PC Card/CompactFlash controller waveforms for attribute memory read access. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 Figure 35. PC Card/CompactFlash controller waveforms for attribute memory write access. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Figure 36. PC Card/CompactFlash controller waveforms for I/O space read access . . . . . . . . . . . . . 75 Figure 37. PC Card/CompactFlash controller waveforms for I/O space write access . . . . . . . . . . . . . 76 Figure 38. NAND controller waveforms for read access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
ListoffiguresSTM32F103xC,STM32F103xD,STM32F103xE.78Figure39.NANDcontrollerwaveformsforwriteaccess..Figure 40.NANDcontrollerwaveformsforcommonmemoryreadaccess.78Figure 41.NANDcontrollerwaveformsforcommonmemorywriteaccess.79..86Figure 42.I/OACcharacteristicsdefinition..86Figure 43.RecommendedNRSTpinprotectionFigure 44.cbusACwaveformsandmeasurementcircuit..89.91Figure 45.SPItimingdiagram-slavemodeandCPHA=0SPI timing diagram - slave mode and CPHA = 1(i)...91Figure 46.SPI timing diagram -master mode(1).92Figure 47.I2s slave timing diagram (Philips protocol)(1).94Figure 48.Figure 49.Ps master timing diagram (Philips protocol)(1).94SDIOhigh-speedmode.95Figure 50.....95Figure 51.SD default mode..97Figure 52.USBtimings:definitionofdata signal riseandfall timeFigure 53.ADCaccuracycharacteristics.100Figure54...101TypicalconnectiondiagramusingtheADCFigure 55.Power supply and reference decoupling (VREF+ not connected to VpDA).101Figure56.Power supply and reference decoupling (VREF+connected to VpDA)..102:104Figure 57.12-bitbuffered/non-bufferedDAC.Figure 58..106RecommendedPCBdesignrules(0.80/0.75mmpitchBGA)Figure 59.LFBGA144 - 144-ball low profile fine pitch ball grid array,10 x 10 mm,0.8 mm pitch,package outline.........107Figure 60.LFBGA100-10x10mmlowprofile finepitchballgridarraypackage...108outline..Figure 61.WLcSP,64-ball4.466x4.395mm,0.500mmpitch,wafer-levelchip-scale..109package outline...Figure 62..110RecommendedPCBdesignrules(0.5mmpitchBGA)Figure 63.LQFP144,20x20mm,144-pinlow-profilequad.111flat package outline.Recommendedfootprint(1)Figure 64..111.112Figure 65.LQFP100,14x14mm100-pinlow-profilequadflatpackageoutlineRecommendedfootprint(1)..112Figure 66.113Figure 67.LQFP64-10x10mm64pinlow-profilequadflatpackageoutlineRecommended footprint(1)Figure 68.113116Figure 69.LQFP100Ppmaxvs.TAS8/123DocID14611Rev7
List of figures STM32F103xC, STM32F103xD, STM32F103xE 8/123 Doc ID 14611 Rev 7 Figure 39. NAND controller waveforms for write access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 Figure 40. NAND controller waveforms for common memory read access . . . . . . . . . . . . . . . . . . . . . 78 Figure 41. NAND controller waveforms for common memory write access. . . . . . . . . . . . . . . . . . . . . 79 Figure 42. I/O AC characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 Figure 43. Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 Figure 44. I2C bus AC waveforms and measurement circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 Figure 45. SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 Figure 46. SPI timing diagram - slave mode and CPHA = 1(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 Figure 47. SPI timing diagram - master mode(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 Figure 48. I2S slave timing diagram (Philips protocol)(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 Figure 49. I2S master timing diagram (Philips protocol)(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 Figure 50. SDIO high-speed mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 Figure 51. SD default mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 Figure 52. USB timings: definition of data signal rise and fall time . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 Figure 53. ADC accuracy characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 Figure 54. Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 Figure 55. Power supply and reference decoupling (VREF+ not connected to VDDA). . . . . . . . . . . . . 101 Figure 56. Power supply and reference decoupling (VREF+ connected to VDDA). . . . . . . . . . . . . . . . 102 Figure 57. 12-bit buffered /non-buffered DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 Figure 58. Recommended PCB design rules (0.80/0.75 mm pitch BGA) . . . . . . . . . . . . . . . . . . . . . 106 Figure 59. LFBGA144 – 144-ball low profile fine pitch ball grid array, 10 x 10 mm, 0.8 mm pitch, package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 Figure 60. LFBGA100 - 10 x 10 mm low profile fine pitch ball grid array package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 Figure 61. WLCSP, 64-ball 4.466 × 4.395 mm, 0.500 mm pitch, wafer-level chip-scale package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 Figure 62. Recommended PCB design rules (0.5 mm pitch BGA) . . . . . . . . . . . . . . . . . . . . . . . . . . 110 Figure 63. LQFP144, 20 x 20 mm, 144-pin low-profile quad flat package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 Figure 64. Recommended footprint(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 Figure 65. LQFP100, 14 x 14 mm 100-pin low-profile quad flat package outline . . . . . . . . . . . . . . . 112 Figure 66. Recommended footprint(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 Figure 67. LQFP64 – 10 x 10 mm 64 pin low-profile quad flat package outline . . . . . . . . . . . . . . . . 113 Figure 68. Recommended footprint(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 Figure 69. LQFP100 PD max vs. TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
STM32F103xC,STM32F103xD,STM32F103xEIntroduction1IntroductionThisdatasheetprovidestheorderinginformationandmechanicaldevicecharacteristicsottheSTM32F103xC,STM32F103xDandSTM32F103xEhigh-densityperformancelinemicrocontrollers.FormoredetailsonthewholeSTMicroelectronicsSTM32F103xxfamilyplease refer to Section 2.2:Full compatibility throughout the family.Thehigh-densitySTM32F103xxdatasheetshouldbereadinconjunctionwiththeSTM32F10xxxreferencemanual.For information on programming,erasing and protectionofthe internal Flashmemoryplease refer to the STM32F10xxx Flash programmingmanual.ThereferenceandFlashprogrammingmanualsarebothavailablefromtheSTMicroelectronicswebsitewww.st.comForinformationontheCortexTM-M3corepleaserefertotheCortexTm-M3TechnicalReferenceManual,availablefromthewww.arm.comwebsiteatthefollowingaddress:http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddio337el.1■ECortexVUARM:IntelligentProcessorsbyARMA9/123Doc ID14611Rev7
STM32F103xC, STM32F103xD, STM32F103xE Introduction Doc ID 14611 Rev 7 9/123 1 Introduction This datasheet provides the ordering information and mechanical device characteristics of the STM32F103xC, STM32F103xD and STM32F103xE high-density performance line microcontrollers. For more details on the whole STMicroelectronics STM32F103xx family, please refer to Section 2.2: Full compatibility throughout the family. The high-density STM32F103xx datasheet should be read in conjunction with the STM32F10xxx reference manual. For information on programming, erasing and protection of the internal Flash memory please refer to the STM32F10xxx Flash programming manual. The reference and Flash programming manuals are both available from the STMicroelectronics website www.st.com. For information on the Cortex™-M3 core please refer to the Cortex™-M3 Technical Reference Manual, available from the www.arm.com website at the following address: http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0337e/
DescriptionSTM32F103xC,STM32F103xD,STM32F103xE2DescriptionTheSTM32F103xC,STM32F103xDandSTM32F103xEperformancelinefamilyincorporates the high-performance ARMCortexTm-M332-bit RISC core operating ata72MHzfrequency,high-speedembeddedmemories(Flashmemoryupto512KbytesandSRAMupto64Kbytes),andanextensiverangeofenhancedI/Osandperipheralsconnected to twoAPBbuses.Alldevicesofferthree 12-bit ADCs,fourgeneral-purpose16-bit timers plus two PwM timers,as well as standard and advanced communicationinterfaces:uptotwoICs,threeSPls,two2Ss,oneSDIO,fiveUSARTs,anUSBandaCAN.TheSTM32F103xxhigh-densityperformancelinefamilyoperates inthe-40to+105Ctemperaturerange, from a 2.0 to3.6Vpower supply.Acomprehensive set of power-savingmodeallowsthedesignoflow-powerapplications.TheSTM32F103xxhigh-densityperformance linefamilyoffersdevices insixdifferentpackagetypes:from64pins to144pins.Dependingon thedevicechosen,different setsofperipherals are included,thedescriptionbelow gives an overviewof thecompleterangeofperipheralsproposedinthisfamilyThesefeaturesmaketheSTM32F103xxhigh-densityperformance linemicrocontrollerfamily suitablefora widerange ofapplications:.Motordriveandapplicationcontrol.MedicalandhandheldequipmentPCperipheralsgamingandGPSplatforms.Industrialapplications,PLC,inverters,printers,andscannersSAlarmsystems,videointercom,andHVACOFigure1showsthegeneralblockdiagramof thedevicefamily.S10/123Doc ID14611Rev7
Description STM32F103xC, STM32F103xD, STM32F103xE 10/123 Doc ID 14611 Rev 7 2 Description The STM32F103xC, STM32F103xD and STM32F103xE performance line family incorporates the high-performance ARM® Cortex™-M3 32-bit RISC core operating at a 72 MHz frequency, high-speed embedded memories (Flash memory up to 512 Kbytes and SRAM up to 64 Kbytes), and an extensive range of enhanced I/Os and peripherals connected to two APB buses. All devices offer three 12-bit ADCs, four general-purpose 16- bit timers plus two PWM timers, as well as standard and advanced communication interfaces: up to two I2Cs, three SPIs, two I2Ss, one SDIO, five USARTs, an USB and a CAN. The STM32F103xx high-density performance line family operates in the –40 to +105 °C temperature range, from a 2.0 to 3.6 V power supply. A comprehensive set of power-saving mode allows the design of low-power applications. The STM32F103xx high-density performance line family offers devices in six different package types: from 64 pins to 144 pins. Depending on the device chosen, different sets of peripherals are included, the description below gives an overview of the complete range of peripherals proposed in this family. These features make the STM32F103xx high-density performance line microcontroller family suitable for a wide range of applications: ● Motor drive and application control ● Medical and handheld equipment ● PC peripherals gaming and GPS platforms ● Industrial applications, PLC, inverters, printers, and scanners ● Alarm systems, video intercom, and HVAC Figure 1 shows the general block diagram of the device family