PM0056TheCortex-M3processorTheprocessorclearstheFAULTMASKbittoOonexitfromanyexceptionhandlerexcepttheNMIhandler.BaseprioritymaskregisterTheBASEPRIregisterdefinestheminimumpriorityforexceptionprocessing.WhenBASEPRIissettoanonzerovalue,itpreventstheactivationofall exceptionswithsameorlowerprioritylevelastheBASEPRIvalue.SeetheregistersummaryinTable2onpage15for its attributes.Figure7showsthebit assignments.Figure7.BASEPRIbitassignments31870ReservedBASEPRIMSv39640V1Table9.BASEPRIregisterbitassignmentsBitsFunctionBits 31:8ReservedBASEPRI[7:4] Priority mask bits(1)Bits 7:4Ox00:no effectNonzero:definesthebasepriorityforexceptionprocessingTheprocessordoesnotprocessanyexceptionwithapriorityvaluegreaterthanorequaltoBASEPRI.Bits 3:0ReservedThis field is similarto the priority fields in the interrupt priorityregisters.See Interrupt priority registers1:(NViCIPRx)onpage125formoreinformation.RememberthafhigherpriorityfieldvaluescorrespondtolowerexceptionprioritiesCONTROLregisterTheCONTROLregistercontrolsthestackusedandtheprivilegelevelforsoftwareexecutionwhen theprocessor is inThreadmode.Seethe registersummaryin Table2onpage15foritsattributes.Figure8showsthebitassignments.Figure8.CONTROLbitassignments31ReservedActive stack pointerThread modeprivilegelevelMS48367V1SDocID15491Rev621/156
DocID15491 Rev 6 21/156 PM0056 The Cortex®-M3 processor 155 The processor clears the FAULTMASK bit to 0 on exit from any exception handler except the NMI handler. Base priority mask register The BASEPRI register defines the minimum priority for exception processing. When BASEPRI is set to a nonzero value, it prevents the activation of all exceptions with same or lower priority level as the BASEPRI value. See the register summary in Table 2 on page 15 for its attributes. Figure 7 shows the bit assignments. Figure 7. BASEPRI bit assignments CONTROL register The CONTROL register controls the stack used and the privilege level for software execution when the processor is in Thread mode. See the register summary in Table 2 on page 15 for its attributes. Figure 8 shows the bit assignments. Figure 8. CONTROL bit assignments Table 9. BASEPRI register bit assignments Bits Function Bits 31:8 Reserved Bits 7:4 BASEPRI[7:4] Priority mask bits(1) 0x00: no effect Nonzero: defines the base priority for exception processing. The processor does not process any exception with a priority value greater than or equal to BASEPRI. 1. This field is similar to the priority fields in the interrupt priority registers. See Interrupt priority registers (NVIC_IPRx) on page 125 for more information. Remember that higher priority field values correspond to lower exception priorities. Bits 3:0 Reserved MSv39640V1 Reserved BASEPRI 31 8 7 0 31 210 Reserved Active stack pointer Thread mode privilege level MS48367V1
TheCortex-M3processorPM0056Table10.CONTROLregisterbitdefinitionsBitsFunctionBits 31:2ReservedBit 1ASPSEL:ActivestackpointerselectionSelects the current stack:O: MSP is the current stack pointer1:PSPisthecurrentstackpointerInHandlermodethisbitreadsaszeroandignoreswritesBit oTPL:Thread mode privilege levelDefines the Thread mode privilege level.O:Privileged1:UnprivilegedTheHandlermodealwaysusestheMSP,sotheprocessorignoresexplicit writestotheactivestackpointerbitoftheCONTROLregisterwheninHandlermode.TheexceptionentryandreturnmechanismsupdatetheCONTROLregister.Inan OS environment,it is recommendedthat threads running inThreadmode usetheprocess stack and thekernelandexceptionhandlers usethemainstackBydefault,Threadmodeuses theMSP.Toswitchthestackpointerused inThreadmodetothePSP,usetheMSRinstructiontosettheActivestackpointerbitto1,seeMSRonpage101.When changingthe stack pointer,softwaremust usean ISB instruction immediatelyafterthe MSR instruction.This ensures that instructions after the ISB execute using thenewstack pointer.SeeISB onpage1002.1.4Exceptions and interruptsTheCortex-M3 processor supports interrupts and systemexceptions.TheprocessorandtheNestedVectored InterruptController(NViC)prioritizeandhandleall exceptions.Anexceptionchangesthenormalflowofsoftwarecontrol.Theprocessoruseshandlermodetohandleallexceptionsexceptforreset.SeeExceptionentryonpage37andExceptionreturnonpage38formoreinformation.The NVIC registers control interrupt handling.See Memory protection unit (MPU) onpage 105formore information.2.1.5DatatypesTheprocessor:Supports the following data types:?32-bit words16-bithalfwords-8-bit bytes一supports 64-bit data transfer instructionsmanagesallmemoryaccesses(datamemory,instructionmemoryandPrivatePeripheralBus(PPB))as little-endian.SeeMemoryregions,typesandattributesonpage25formore information.A22/156DocID15491Rev6
The Cortex®-M3 processor PM0056 22/156 DocID15491 Rev 6 The Handler mode always uses the MSP, so the processor ignores explicit writes to the active stack pointer bit of the CONTROL register when in Handler mode. The exception entry and return mechanisms update the CONTROL register. In an OS environment, it is recommended that threads running in Thread mode use the process stack and the kernel and exception handlers use the main stack. By default, Thread mode uses the MSP. To switch the stack pointer used in Thread mode to the PSP, use the MSR instruction to set the Active stack pointer bit to 1, see MSR on page 101. When changing the stack pointer, software must use an ISB instruction immediately after the MSR instruction. This ensures that instructions after the ISB execute using the new stack pointer. See ISB on page 100 2.1.4 Exceptions and interrupts The Cortex-M3 processor supports interrupts and system exceptions. The processor and the Nested Vectored Interrupt Controller (NVIC) prioritize and handle all exceptions. An exception changes the normal flow of software control. The processor uses handler mode to handle all exceptions except for reset. See Exception entry on page 37 and Exception return on page 38 for more information. The NVIC registers control interrupt handling. See Memory protection unit (MPU) on page 105 for more information. 2.1.5 Data types The processor: • Supports the following data types: – 32-bit words – 16-bit halfwords – 8-bit bytes • supports 64-bit data transfer instructions. • manages all memory accesses (data memory, instruction memory and Private Peripheral Bus (PPB)) as little-endian. See Memory regions, types and attributes on page 25 for more information. Table 10. CONTROL register bit definitions Bits Function Bits 31:2 Reserved Bit 1 ASPSEL: Active stack pointer selection Selects the current stack: 0: MSP is the current stack pointer 1: PSP is the current stack pointer. In Handler mode this bit reads as zero and ignores writes. Bit 0 TPL: Thread mode privilege level Defines the Thread mode privilege level. 0: Privileged 1: Unprivileged
PM0056TheCortex-M3processor2.1.6TheCortex?microcontrollersoftware interfacestandard (CMSIS)ForaCortex-M3microcontrollersystem,theCortexMicrocontrollerSoftwareInterfaceStandard(CMSIS)defines:Acommonwayto:AccessperipheralregistersDefineexceptionvectorsThe names of:Theregisters of the core peripheralsThecoreexceptionvectorsAdevice-independent interface for RTOs kernels, including a debug channelTheCMSiSincludesaddressdefinitionsanddatastructuresforthecoreperipherals intheCortex-M3processor.Italsoincludesoptional interfacesformiddlewarecomponentscomprisingaTcP/IPstackandaFlashfilesystem.CMSiSsimplifiessoftwaredevelopmentbyenablingthereuseoftemplatecodeandthecombinationofCMSiS-compliantsoftwarecomponentsfromvariousmiddlewarevendorsSoftwarevendorscanexpandtheCMSiStoincludetheirperipheraldefinitionsandaccessfunctions forthoseperipherals.Thisdocument includestheregisternamesdefinedbytheCMSiS,andgivesshortdescriptionsoftheCMSiSfunctionsthataddresstheprocessorcoreandthecoreperipherals.This document uses the register short names defined by the CMSiS. In a few cases thesedifferfromthearchitectural shortnamesthat mightbeused inotherdocumentsThefollowingsectionsgivemoreinformationabouttheCMSiSSection 2.5.4: Power management programming hints on page 43Intrinsic functions on page 49The CMSIS mapping of the Cortex-M3 NVIC registers on page 119NviC programming hints onpage127A23/156DocID15491Rev6
DocID15491 Rev 6 23/156 PM0056 The Cortex®-M3 processor 155 2.1.6 The Cortex® microcontroller software interface standard (CMSIS) For a Cortex-M3 microcontroller system, the Cortex Microcontroller Software Interface Standard (CMSIS) defines: • A common way to: – Access peripheral registers – Define exception vectors • The names of: – The registers of the core peripherals – The core exception vectors • A device-independent interface for RTOS kernels, including a debug channel The CMSIS includes address definitions and data structures for the core peripherals in the Cortex-M3 processor. It also includes optional interfaces for middleware components comprising a TCP/IP stack and a Flash file system. CMSIS simplifies software development by enabling the reuse of template code and the combination of CMSIS-compliant software components from various middleware vendors. Software vendors can expand the CMSIS to include their peripheral definitions and access functions for those peripherals. This document includes the register names defined by the CMSIS, and gives short descriptions of the CMSIS functions that address the processor core and the core peripherals. This document uses the register short names defined by the CMSIS. In a few cases these differ from the architectural short names that might be used in other documents. The following sections give more information about the CMSIS: • Section 2.5.4: Power management programming hints on page 43 • Intrinsic functions on page 49 • The CMSIS mapping of the Cortex®-M3 NVIC registers on page 119 • NVIC programming hints on page 127
TheCortex-M3processorPM00562.2Memory modelThissectiondescribestheprocessormemorymap,thebehaviorofmemoryaccesses,andthebit-bandingfeatures.Theprocessorhasafixedmemorymapthatprovidesupto4GBofaddressablememory.Figure9.MemorymapOxFFFFFFFFVendor-specific511MBmemory0xE0100000OXEOOFFFFFPrivate peripheral1.0MBbus0xE0000000OxDFFFFFFF1.0GBExternal device0xA00000000x9FFFFFFFExternal RAM1.0GB0x43FFFFFF32MBBitbandalias0x600000000x420000000x5FFFFFFF0.5GBPeripheral0x400FFFFF1MBBitband region0x400000000x400000000x3FFFFFFF0x23FFFFFFSRAM0.5GB32MB Bit band alias0x200000000x220000000x1FFFFFFFCode0.5GB0x200FFFFF1MBBit band region0x200000000x00000000MS48368V1TheregionsforSRAM andperipherals include bit-bandregions.Bit-bandingprovidesatomic operations to bit data,see Section 2.2.5:Bit-banding onpage27.The processor reserves regions of thePrivateperipheral bus (PPB)address rangefor coreperipheralregisters,seeSection4.1:AbouttheSTM32coreperipheralsonpage105.A24/156DocID15491Rev6
The Cortex®-M3 processor PM0056 24/156 DocID15491 Rev 6 2.2 Memory model This section describes the processor memory map, the behavior of memory accesses, and the bit-banding features. The processor has a fixed memory map that provides up to 4 GB of addressable memory. Figure 9. Memory map The regions for SRAM and peripherals include bit-band regions. Bit-banding provides atomic operations to bit data, see Section 2.2.5: Bit-banding on page 27. The processor reserves regions of the Private peripheral bus (PPB) address range for core peripheral registers, see Section 4.1: About the STM32 core peripherals on page 105. Vendor-specific memory External device External RAM Peripheral SRAM Code 0xFFFFFFFF Private peripheral bus 0xE0100000 0xE00FFFFF 0x9FFFFFFF 0xA0000000 0x5FFFFFFF 0x60000000 0x3FFFFFFF 0x40000000 0x1FFFFFFF 0x20000000 0x00000000 0x40000000 Bit band region 32MB Bit band alias 1MB 0x400FFFFF 0x42000000 0x43FFFFFF Bit band region 32MB Bit band alias 1MB 0x20000000 0x200FFFFF 0x22000000 0x23FFFFFF 1.0GB 1.0GB 0.5GB 0.5GB 0.5GB 0xDFFFFFFF 0xE0000000 1.0MB 511MB MS48368V1
PM0056TheCortex-M3processor2.2.1Memory regions,types andattributesThememorymapsplitsthememorymapintoregions.Eachregionhasadefinedmemorytype,and someregions haveadditionalmemory attributes.Thememorytypeandattributesdeterminethebehaviorofaccessestotheregion.Thememorytypesare:NormalTheprocessorcanre-ordertransactionsforefficiency,orperformspeculativereadsDeviceTheprocessorpreservestransaction orderrelativetoothertransactions to Device or Strongly-ordered memory.Strongly-orderedTheprocessorpreserves transactionorderrelativetoallothertransactions.ThedifferentorderingrequirementsforDeviceandStrongly-orderedmemorymeanthatthememorysystemcanbufferawritetoDevicememory,butmustnotbufferawritetoStronglyordered memory.The additional memory attributes include:ExecuteNever(XN)Meanstheprocessorpreventsinstructionaccesses.AnyattempttofetchaninstructionfromanXNregioncausesamemorymanagementfaultexception.2.2.2MemorysystemorderingofmemoryaccessesFormostmemoryaccesses caused by explicit memoryaccess instructions, thememorysystemdoes notguaranteethat theorderin which theaccesses completematches theprogramorderofthe instructions,providingthisdoes notaffectthebehavioroftheinstructionsequence.Normally,ifcorrectprogramexecutiondependsontwomemoryaccessescompletinginprogramorder,softwaremust insertamemorybarrierinstructionbetweenthememoryaccessinstructions,seeSection2.2.4:Softwareorderingofmemoryaccessesonpage26However,thememorysystemdoesguaranteesomeorderingofaccessestoDeviceandStrongly-orderedmemory.FortwomemoryaccessinstructionsA1andA2,ifA1occursbeforeA2inprogramorder,theorderingofthememoryaccessescausedbytwoinstructions is:Table 11. Ordering of memory accesses(1)A2A1DeviceaccessStrongly orderedNormalaccessaccessNon-shareableShareableNormalaccess---.Deviceaccess,VVnon-shareable21Deviceaccess,shareable<<<Strongly ordered accessmeans that the memory systemdoes not guarantee theorderingofthe accesses.<meansthataccessesareobservedinprogramorder,thatis,AiisalwaysobservedbeforeA2A25/156DocID15491Rev6
DocID15491 Rev 6 25/156 PM0056 The Cortex®-M3 processor 155 2.2.1 Memory regions, types and attributes The memory map splits the memory map into regions. Each region has a defined memory type, and some regions have additional memory attributes. The memory type and attributes determine the behavior of accesses to the region. The memory types are: The different ordering requirements for Device and Strongly-ordered memory mean that the memory system can buffer a write to Device memory, but must not buffer a write to Stronglyordered memory. The additional memory attributes include: 2.2.2 Memory system ordering of memory accesses For most memory accesses caused by explicit memory access instructions, the memory system does not guarantee that the order in which the accesses complete matches the program order of the instructions, providing this does not affect the behavior of the instruction sequence. Normally, if correct program execution depends on two memory accesses completing in program order, software must insert a memory barrier instruction between the memory access instructions, see Section 2.2.4: Software ordering of memory accesses on page 26. However, the memory system does guarantee some ordering of accesses to Device and Strongly-ordered memory. For two memory access instructions A1 and A2, if A1 occurs before A2 in program order, the ordering of the memory accesses caused by two instructions is: Normal The processor can re-order transactions for efficiency, or perform speculative reads. Device The processor preserves transaction order relative to other transactions to Device or Strongly-ordered memory. Strongly-ordered The processor preserves transaction order relative to all other transactions. Execute Never (XN) Means the processor prevents instruction accesses. Any attempt to fetch an instruction from an XN region causes a memory management fault exception. Table 11. Ordering of memory accesses(1) 1. - means that the memory system does not guarantee the ordering of the accesses. < means that accesses are observed in program order, that is, A1 is always observed before A2. A1 A2 Normal access Device access Strongly ordered access Non-shareable Shareable Normal access - - - - Device access, non-shareable -<- < Device access, shareable - - < < Strongly ordered access - < < <